I have a packet communication via 2 devices over SPI
At the end of some packets I receive some extra clocks via SPI, therefore it corrupts the next packet. Situation can be discovered by BUSY flag set. Datasheet says it is cleared by hardware. Is there a way to clear the flag by software?
I assume slave mode with dma in stm32l4 type device having SPI generation with hw 32 bit fifo which can't be flushed unless spi is reset by sys rcc reset bit, and reconfigured.
