Posted on July 01, 2015 at 19:37In general separate I and D buses to a memory array are needed because code and data often do not originate on the same cache line. Code is (mostly) sequential so a cache hit is likely on subsequent instruction fetches. Data behaves differently, more random access and in a different area than code. So the cache line for data is independent of instruction cache line.
For the M3 the cache is minimal, and the M4 (for the STM series) only marginally larger. But the M4 cores can support much larger caches and on some vendors using the ARM big.LITTLE technology you will see L1 cache on an M4 as large as 32K, so the dual bus is significant to the core IP design. As you move up the embedded ARM models the cache becomes a major performance feature (M7, A5, A7, etc.).
For the STM32F4 the dual bus has some other advantages when optimizing for the bus matrix. Offloading data access to CCM or SRAM reduces contention with flash, but the D bus still lets you use DMA, running in parallel with the CPU, to transfer from flash to a peripheral or SRAM. And if you use the SRAM2 bank for DMA you don't lose the D cache line.
Jack Peacock
