Posted on May 14, 2015 at 16:01
My logic analyser shows that 76800 writes (320x240) are happening on the 8080 bus, its just that the SSD stops listening. If I change the colour of the box to another colour, say yellow, then the whole screen updates successfully.
Once again, the logic analyser shows 76800 writes from the FMC, yet this time the whole screen is refreshed correctly. I can get the white square to draw correctly by lowing the HCLK speed of the micro (by using /8 in pll-p). If I use 84MHz (PLL-P = /4) I can get the white square to draw correctly by putting a 1K pullup between the NWE line and +V. The pullup doesn't work when HCLK is 168MHz, the only way I can get this to work is to enable the 'extended mode' on the FMC controller, though the screen refreshes are very slow when I do this, even though I'm using the same timing structure for both normal and extended mode. The problem seems to exist if regardless of if I use external or internal SDRAM for the frame buffer. Most of the time I'm using an internal buffer because it allows me to analyse the FMC port easier with the logic analyser. I'm not sure if a port isn't set up correctly or some other timing isn't correct, but if you find anything out I would be interested to know.
I am also having a possible similar / related problem. For testing I'm drawing a square onto a plain background in a frame buffer, then transferring the buffer to the screen though the FMC (not using dma). If the colour of the square is white, then the SSD1963 chip stops listening to the transfer partway though the update as show here:
My logic analyser shows that 76800 writes (320x240) are happening on the 8080 bus, its just that the SSD stops listening. If I change the colour of the box to another colour, say yellow, then the whole screen updates successfully. Once again, the logic analyser shows 76800 writes from the FMC, yet this time the whole screen is refreshed correctly. I can get the white square to draw correctly by lowing the HCLK speed of the micro (by using /8 in pll-p). If I use 84MHz (PLL-P = /4) I can get the white square to draw correctly by putting a 1K pullup between the NWE line and +V. The pullup doesn't work when HCLK is 168MHz, the only way I can get this to work is to enable the 'extended mode' on the FMC controller, though the screen refreshes are very slow when I do this, even though I'm using the same timing structure for both normal and extended mode. The problem seems to exist if regardless of if I use external or internal SDRAM for the frame buffer. Most of the time I'm using an internal buffer because it allows me to analyse the FMC port easier with the logic analyser. I'm not sure if a port isn't set up correctly or some other timing isn't correct, but if you find anything out I would be interested to know.
