SRAM on a 100-pin STM32F103

[donald23]

Posted on October 31, 2011 at 19:50

I have been reviewing the AN2783 for insight about connection upto 1MB of RAM to the STM32F103 100-pin device.

I am trying to figure out how to connect this device to a static RAM device. The AN2783 document is not clear about what RAM chip I can use or how to connect Address latches to the RAM devices. Is there a document that better explains how this works ? Thanks you Donald

[Tesla DeLorean]

Posted on November 01, 2011 at 01:19

If you are using a single device you should be able to directly attach an 8 or 16-bit part to the FSMC. The size depends on the address bits you want to use. The STM32 also internally shifts the address bus depending on the data width, so A0 will always be the lowest order address bit (in 16-bit it will connect to the core's A1)

Suggest you pull the manuals for a couple of the STM3210 eval boards, several of them have SRAM, with schematics, and initialization code. Be aware that it will be relatively slow compared to internal SRAM, so use it as storage, not to execute code, or store stack data.

[infoinfo980]

Posted on November 01, 2011 at 22:14

I think Donald is asking about how to connect up a SRAM to the 100 pin version of the F103 where the data lines are muxed with the address lines. This necessitates the use of a latch to hold the address lines steady during the second part of the memory transaction when the data is transferred. This in turn requires the host device to output a latch enable signal at the appropriate instant.

Nowhere in the publically available documentation can I see where they document where this line is for the NOR/SRAM banks (they are documented for NAND) and all the dev boards that have SRAM are 144 pin devices. It would be nice if someone from ST could chip in here...