Posted on May 17, 2011 at 13:19I have an application where I need 3 SPI master ports. I'm using the STM32F103RE. Since the SPI3 pins are shared with the JTAG port, SPI3 is useless to me. I'm using SPI1 and SPI2 as SPI masters, and USART3 in synchronous mode as an SPI master.
The nSS pins for SPI1&2 are not used. I have the GPIO pins configured as general purpose inputs (not AF outputs) for other uses. The slave select lines to my slave chips are driven from other GPIO pins by software. For USART3, I have remapped it to use PC10, PC11 and PC12, and the slave select line for the slave IC is driven from another GPIO pin by software.
My concern is the errata that mentions USART3+SPI2. To me, it is not clear what will happen in my circumstance. I am not using PB12 as an AF output, and I have USART3 mapped to PC10, PC11 and PC12. Will I still run into issues with this configuration? Will USART3 in fact output the clock on PC12? If I am not using PB12 as the nSS pin (and it is not configured as AF output) what happens if I must set nSS to be an output in the SPI registers but don't configure the GPIO for AF output?
