spi1 bus with multiple slave is possible?

[MDeva.1]

Mostly our spi will use these 3 signals (SCK, MISO, NSS (CS) ) in master rx only mode. where multiple slave are connected to SPI and each will have a dedicated CS in star topology as shown above.

How to select this NSS/CS pin for individual slave, can we switch this signal at 10Mhz where sclk=25Mhz.

is there any restriction when using multiple slave on single bus? please help me.

[TDK]

> How to select this NSS/CS pin for individual slave, can we switch this signal at 10Mhz where sclk=25Mhz.

You configure the CS pin as a GPIO output and toggle it manually. Set it low before the transaction and high afterwards.

Toggling it automatically at 10 MHz isn't an option.

> is there any restriction when using multiple slave on single bus? please help me.

No, only pin availability.

[MDeva.1]

we are operating SPI at 75Mhz and expects that CS will toggle at 6-10Mhz. is that okey with multiple slave (x4) ...or CS will be a bottle neck? or can use timers with CS??

[TDK]

Toggling CS automatically at 6-10 MHz isn't an option. You could use a timer output for CS, but it would be difficult to sync that with the SPI stream. The STM32 isn't really built for high speed SPI transactions with tight timing like this.

[MDeva.1]

@TDK​ 

Can you please help how can I do this can you suggest how I can achieve this?

[TDK]

You haven't clearly described the functionality you're looking for. Draw a timing diagram of the desired waveform.