SPI transactions of greater than 16 bits

[gavin2]

Posted on August 16, 2012 at 16:27

Hi,

I am looking for recommendations as to how best to deal with SPI transactions where the SPI word length is greater than 16 bits.

I intend to use 64 bit transactions from the host PC to my stm32 board. Therefore, I expect the SPI will interrupt 4 times (if the SPI data size is set to 16). Could I create a counter incremented by the interrupt, wait until the count = 4, then process the 64 bits together? This seems to make sense to me but I guess there would be a problem if the counter was to get out of sync with the transactions from the host.

Are there any suggested or more neater methods of dealing with SPI transactions of greater than 16 bits?

Thanks in advance

[Tesla DeLorean]

Posted on August 16, 2012 at 16:39

Or presumably use DMA, and key off the RX DMA TC?

[gavin2]

Posted on August 16, 2012 at 16:54

Hi,

Thanks for your input.I am afraid I dont follow. Could you be a little bit more precise? I am yet to use the DMA stuff some am not too knowledgeable about its usage.Thanks again

[Tesla DeLorean]

Posted on August 16, 2012 at 17:32

I am afraid I dont follow. Could you be a little bit more precise? I am yet to use the DMA stuff some am not too knowledgeable about its usage.

Sorry, I just didn't want to get sucked into implementation. Both receive and transmit have separate channels, I'd recommend waiting on the RX TC (Terminal Count) as this will occur after the last bit has been received, and thus the timing will not be obscured by the TX side buffering. You'll need to review the SPI and DMA examples provided in the ST libraries for your specific/unspecified chip, and review the manuals to understand the DMA channel/stream routing for the SPIx chosen. See the ''DMAx request mapping'' tables in the STM32F4 reference manual, for example. Implement 8-byte SPI DMA transactions, get a single interrupt when done, and avoid dealing with the SPI interrupts at a byte/half-word level.

[gavin2]

Posted on August 16, 2012 at 17:37

Hi,

That sounds very interesting and along the lines of what I am looking for. I will investigate further the examples you have pointed me to.Thanks and regards

[Tesla DeLorean]

Posted on August 16, 2012 at 17:57

As to your synchronization question.

How do anticipate this will occur? How do you detect when it occurs? Do you have any synchronization signal, like CS? Does the data have a synchronization pattern, or self-synchronizing properties?

[gavin2]

Posted on August 17, 2012 at 13:03

Hi,

Much of this is still to be decided. All I know for sure is that I will be sending packets of bytes (probably around 8 bytes) across the SPI at a time.The data from the host could be at any time but I will probably tie it to a clock on the host so the transactions happen at regular intervals.Yes, I do intend to use CS, although at the moment, I am not. I just use the SPI interrupt to indicate that 8/16 bits have been received.No, there is no sync pattern within the transmitted data but there could be in the future. I have not ruled this out.It has been useful for you to ask me these questions as these are all the things I have been asking myself. In the short term, I am looking for a simple and robust method of sending more than 2 bytes across the SPI at a time. This DMA approach you have suggested may be useful to me. I will look at that shortly but if you have any other references, then they would be appreciated.Thanks again clive1

[emalund]

Posted on August 17, 2012 at 15:26

I am looking for recommendations as to how best to deal with SPI transactions where the SPI word length is greater than 16 bits.

the usual method is a circular buffer Erik

[gavin2]

Posted on August 17, 2012 at 16:41

Hi Erik,

So I assume you are suggesting you the DMA approach as well?Thanks in advance

[emalund]

Posted on August 17, 2012 at 17:50

not really, that will be your choice to make

Erik