Question
SPI half duplex slave transmit, data shifted / loses sync when using CLK Phase 2
MCU: STM32F411CEU6
IDE: Cube IDE v1.6.1
Init code (Only CLKPhase changes between tests, 1=Leading edge, 2 =Trailing edge):
static void MX_SPI1_Init(void){
hspi1.Instance = SPI1;
hspi1.Init.Mode = SPI_MODE_SLAVE;
hspi1.Init.Direction = SPI_DIRECTION_1LINE;
hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
hspi1.Init.NSS = SPI_NSS_SOFT;
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
hspi1.Init.CRCPolynomial = 10;
if (HAL_SPI_Init(&hspi1) != HAL_OK)
{
Error_Handler();
}
}Test:
volatile uint8_t msg[20]={ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 };
void main(void){
// HAL Init, etc ...
if(HAL_SPI_Transmit(&hspi1, msg, 12, HAL_MAX_DELAY) != HAL_OK){
asm("nop"); // Stop here if not ok (Always OK)
}
while(1);
}After starting HAL_SPI_Transmit, I send train of pulses.
The slave sends only 1s for easier detection.
CLKPhase = 1: Works ok. Also works with both clock polarities.
CLKPhase = 2: The data shifts and loses sync. Happens with both clock polarities.
I thought I was being too fast.
So I tried adding 1mS delay between clocks (Byte - delay - Byte - delay ...) but the result was the same.
Might this be related?
https://github.com/ARMmbed/mbed-os/issues/10589
Althought I checked the HAL code and it seems correct.
