Posted on December 19, 2016 at 19:16We are using a STM32F769 to drive a 400x400 DSI display. What could we do to about double the current writing speed or to identify what is the bottleneck? LTDC is set up for sending data from SRAM1 for DSIHOST that is running in Adapted Command Mode.
Drawing works ok but is limited to about 35 Frames Per Second, which with 24bit pixels and one display data lane is about 135 Mbps (when DSI should be capable of 500).
The problem does NOT seem to be LTDC clocking or DSI line speed: Slowing down the clocks for LTDC (APB2 and PLLSAI1) does not significantly affect the performance. Neither does changing the PLL DSI dominate the performance (with 125 Mbps DSI line speed 19fps, with 250 Mbps 27fps).
Changing HCLK linearly changes the DSI performance, even when keeping PLLDSI, PLLSAI1 and APB2 the same. In this testing we send the same frame buffer without drawing to it so there is no MCU computation load or significant memory/AHB access. The code waits for DSI interrupt to call
HAL_DSI_EndOfRefreshCallback().
I have failed to understand what causes this slow speed: The internal RAM read speed (tried at HCLK 104-216 MHz) or LTDC FIFO should not limit the DSI speed? Shouldn't the AHB memory reading for LTDC and the LTDC writing for DSI be non-conflicting?
The update speed has never exceeded 38 Frames Per Second. From DSI line speed (500 MHz, one data line) theoretically it should be able to update at >100fps. DSI is forced to high speed mode, MCU sleeping has been disabled. LTDC is doing a RGB565->RGB888 conversion but that does not seem to affect the speed either.STM32Cube_FW_F7_V1.4.0 libraries were used. Upgrading to STM32Cube_FW_F7_V1.5.1 did not change the speed. Changing the LTDC to read from internal Flash memory did not make any difference either.Pertti
