Setting SPI1 freq for SD card = 24Mhz

[aamirali641989]

Posted on June 17, 2013 at 12:32

I am using STM32F205 with 120Mhz interanl PLL(HSI).

I have to interface SD Card on SPI with <= 24Mhz. Problem is with 120Mhz sysclk I can only obtain SPI-30Mhz(can't use of SD), 15Mhz(too slow)and other lower freq.Now there is trade-off b/w SPI freq & SYSCLK. The best settings I can think is SYSCLK = 96Mhz & SPI = 24Mhz . Can anyone give better solution or any solution in which I don't have to sacrifice SYSCLK freq. 

[Tesla DeLorean]

Posted on June 17, 2013 at 13:48

SDIO it 1-bit mode?

[aamirali641989]

Posted on June 17, 2013 at 14:36There are some compatibility issues with my previous project. So I am left with this option only.Thanx 

[Tesla DeLorean]

Posted on June 17, 2013 at 16:02

That's a pity, because the SDIO controller can drive MicroSD cards like a rocket. Have some Ultra cards pushing 9MBps Write / 18 MBps Read.

The clocking options in the STM32 parts sadly limits them quite significantly.

[alexandr]

Posted on June 17, 2013 at 17:46

Hello,

Clive, you got these numbers with 8bit SDIO @ 24MHz without divider bypass and without HW flow? (As HW flow and bypass are not working, according the Errata) Thanks, Alex.

[Tesla DeLorean]

Posted on June 17, 2013 at 18:42

I pulled those doing 4-bit, 48 MHz, Bypassed, on SDXC (not v2 spec cards). The read/write were validated to have correctly transferred from/to the card correctly.

The interface can also be clocked above 48 MHz.

[alexandr]

Posted on June 17, 2013 at 20:31

So, it is possible to use bypass in F2xx/F4xx, nevertheless of errata?

[Tesla DeLorean]

Posted on June 17, 2013 at 21:41

So, it is possible to use bypass in F2xx/F4xx, nevertheless of errata?

Indeed. The issue isn't with the bypass circuit, which is without doubt a simple mux of the 1x signal and the /2 to N coming from the divider. The errata lacks a lot of detail which would be useful for analysis, but impacts all F2 and F4 parts through the 439. One of the other tidbits is that you can clock the interface up to 75 MHz, with a resultant SDIO bus clock of 37.5 MHz. This can be interpreted two ways, either the circuit has some critical path limiting it to that, or that the 37.5 MHz is around the point where the V2 timing spec is violated. I wouldn't clock full size SD cards, even Ultra/Extreme 45MBps ones, at that speed, but MicroSD cards are rated for 50 MHz SPI operation and MicroSDXC go to 100-200 MHz There are other flaws in the demo software which will cause more damaging behaviour than the expressed errata.