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Set PLL as the system clock for STM32F401RE board

DJ1
Associate III

Here i am trying to set PLL as the system clock using HSI of 16MHz for STM32F401RE development board, but the moment i enable the "SET PLL as system clock" bit, the system gets reset. What can be the reason for this. I am trying to achieve 70 MHz of frequency. 

Below is the code for the same.

 

 

int main()
{
// Clear the default 192 setting
RCC->PLLCFGR &= ~(192 << 6);
// Set 200 to PLLN
RCC->PLLCFGR |= (216 << 6);
// Clear the default 16 setting
RCC->PLLCFGR &= ~(16 << 0);
// Set 8 to PLLM
RCC->PLLCFGR |= (8 << 0);
// Set PLLP to 6
RCC->PLLCFGR |= (2 << 16);
 
// Turn on PLL from RCC CR Register
RCC->CR |= (1 << 24);
// SET PLL as system clock
RCC->CFGR |= (2 << 0);
// Wait while the status flag is set
while(!(RCC->CFGR >> 2 & 2));
 
 
while(1)
{
 
}
}
12 REPLIES 12
DJ1
Associate III

Yes if I try Cube MX than it is working fine but if I am using the same PLLM, PLLP and PLLN bits for 16MHz, the code is not working fine, the moment I run the code, it jumps out from the debugging mode. I don't understand what I am doing wrong.


@DJ1 wrote:

I have kept while loop until the HSIRDY and PLLRDY bits are SET to 1. Even after that the moment i run my code in debug mode, it comes out of debugging.


I asked if you are programming the appropriate wait states. I don't think this response answers that question, and I don't see you doing it in the code.

If you're not setting wait states, that explains why the code is crashing.

If you feel a post has answered your question, please click "Accept as Solution".

As @TDK said above, you need to set FLASH waitstates first.

And you may need to set VOS in PWR, too.

Also check if all VSS/VDD pins are properly connected (including the analog ones), and also if there is a proper capacitor connected to VCAP pin(s).

JW