2025-07-29 4:07 PM - last edited on 2025-09-03 4:21 AM by mƎALLEm
Hi, I have problem config LTDC for 1280x720 @60Hz. Without caching it works no problem, but slow.
We are using 32MB SDRAM 16bit, config at 100MHz. When we use MPU to cache SDRAM, code as below:
```
MPU_Region_InitTypeDef MPU_InitStruct;
/* Disable the MPU */
HAL_MPU_Disable();
// Region 0: All 32MB cached
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.BaseAddress = 0x60000000;
MPU_InitStruct.Size = MPU_REGION_SIZE_32MB;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER0;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.SubRegionDisable = 0x00;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
// Region 1: Last 4MB as non-cacheable for LTDC
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.BaseAddress = 0x61C00000;
MPU_InitStruct.Size = MPU_REGION_SIZE_4MB;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER1;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;//MPU_TEX_LEVEL1;
MPU_InitStruct.SubRegionDisable = 0x00;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/* Enable the MPU */
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
```
Last 4MB we use for LTDC frame buffer. Image shown on screen is good.
But when we write somewhere first 28MB (I dont touch on 4MB ltdc), then the screen has flicker or bad.
The configuration for LTDC 1280x720 is same as ST recommend, pixel clock 74.4MHz... I think this configuration is good because image shown well on monitor without SDRAM cache. Even using MPU cache, image still shown good, as long as I don't write read/write to SDRAM on first 28MB.
Is MPU configuration above good to SDRAM and ltdc?
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2025-09-03 2:34 AM
Hello @Dat Tran ;
Are you using the DMA2D?
Could you please try to decrease the pixel clock? Is the issue solved?
I recommend you to look at AN4861 Introduction to LCD-TFT display controller (LTDC) on STM32 MCUs may help you to check the issue.
Thank you.
Kaouthar
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