STM32H7S3L8 Dual ADC Multichannel + DMA

[htxy]

Hello guys,

for my bachelors project I have decided to build an embedded signal monitoring and classification tool, based on the STM32H7S3L8 Nucleo dev board (NUCLEO H7S3L8). I want to use all  14 available channels of the 2 adcs (technically each ADC has 14, but then pin assignments are shared, which is not beneficial) and i want to let the ADCs stream the data via HPDMA in the SDRAM. Unfortioutly I came across many problems with the configuration and programming, especially with clock configuration of the ADC+DMA in the scanning mode. 

Do some of you already have a working solution to the DMA placement in SDRAM (0x300000 32kB I believe) and with working ADCs you would like to share. 

Also, do you enable callbacks in that case?

Usually I would share my config and code and ask for help to the specific problem, but as I am not at home and already lost my mind with this ******* DMA I might try it that way.

Thanks so much and happy holidays !

[mƎALLEm]

Hello,

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@htxy wrote:

Do some of you already have a working solution to the DMA placement in SDRAM (0x300000 32kB I believe) and with working ADCs you would like to share. 

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First, I don't know from which document you get that information: SDRAM has that address range (0x300000)?

SDRAM memory range is located at that memory range according to the RM0477 / Figure 3. Memory map:

Second, start to configure SDRAM: start by this knowledge base article: How to set up the FMC peripheral to interface with the SDRAM IS42S16800F-6BLI from ISSI

Then do read/write access to the SDRAM. If all are ok start doing a DMA transfers from/to SDRAM and ensure you configure the correct MPU config for data coherency between CPU/DMA:

- AN4839 "Level 1 cache on STM32F7 Series and STM32H7 Series"

- AN4838  "Introduction to memory protection unit management on STM32 MCUs"

Then move on with ADC transfers to SDRAM.

Hope that helps at some points.