SDIO TX underrun because of DMA FIFO error

[rerayne]

Posted on October 05, 2012 at 15:03

Hello,

we are trying to work with SDIO at our FreeRTOS project, Without FreeRTOS everything works fine @ 16 MHz with Transcend miscroSDHC card, but if we try to do same test as FreeRTOS thread, we get TX underrun condition at write to SD @ frequences above 10 MHz. TX underrun condition caused by FIFO error at DMA stream.Does anyone know, how we can achieve full-speed transfer for FreeRTOS? #sdio-dma-underrun-error #details-please

[Tesla DeLorean]

Posted on October 05, 2012 at 18:11

Not much to work with here. Any particular chip, board or settings?

You could check the DMA priority, burst and FIFO settings, and confirm that you are using 32-bit aligned buffers. You could check that you have a suitable clocking scheme for APB1, APB2 and SDIOCLK that meets the timing speeds and requirements to work together properly.

[Moritz M]

Posted on November 14, 2012 at 19:11

Hi li.rayne,

having the same problem with TX underrun I want to know if you haved solved the problem.Regards Moritz

[Tesla DeLorean]

Posted on November 14, 2012 at 20:01

having the same problem with TX underrun I want to know if you haved solved the problem.

A similar problem perhaps, maybe we can pin down what hardware and settings are being used here too? Absent the ability to duplicate, providing some specificity might at least permit others to suggest probable causes, and thus arrive at some solution.

[Moritz M]

Posted on November 22, 2012 at 17:10

I'm using the STM32F103 at 8 MHz with FreeRTOS. The DMA is used for the ADC1, SPI1_RX and SPI1_TX and SDIO. SDIO_CK is 8/3 MHz and PCLK2 1 MHz. 

van_hooft.frank found that it is problematic, when using 3 peripherals with DMA on the STM32F2xx [1] and the TX FIFO underruns when the SDIO interrupts not having the highest priority [2]. I think, the problems are similar to these on the STM32F1xxSo my workaround is:1. Putting SDIO_DataConfig and SDIO_DMACmd in an critical section, together with setting the NVIC-IRQ priority temporarily to 1. 2. Only writing to the SD-Card, when SPI and ADC is not used.With this my FIFO underruns are occurring less often.[1] 

http://blog.frankvh.com/2012/01/13/stm32f2xx-stm32f4xx-dma-maximum-transactions/

[2] 

http://blog.frankvh.com/2011/12/30/stm32f2xx-stm32f4xx-sdio-interface-part-2/

[sdellinger]

Posted on August 27, 2014 at 20:27

I observed this problem with TX underruns on the STM32F4 also. Upon further investigation, it appears that the DMA FIFO Error (FEIF) gets set almost immediately after setting up the DMA, CPSM, and DPSM for transmission to the card. I don't believe ST's StdPeriph library code checks for this condition, but they do suspiciously clear the FEIF flag alongside the DMA Transfer Complete (TC) flag in the SD_ProcessDMAIRQ() interrupt...

void SD_ProcessDMAIRQ(void) {   if(DMA2->LISR & SD_SDIO_DMA_FLAG_TCIF)   {     DMAEndOfTransfer = 0x01;     DMA_ClearFlag(SD_SDIO_DMA_STREAM, SD_SDIO_DMA_FLAG_TCIF|SD_SDIO_DMA_FLAG_FEIF);   <<<<-----  SD_SDIO_DMA_FLAG_FEIF!!!   } } I found that if you detect the FEIF error in the DMA, and immediately clear it, then everything seems to proceed OK and the SDIO never sets the TX underrun flag. I guess that the DMA FIFO problem isn't bad unless it propagates to the SDIO peripheral, because it appears that all the data read back from the SD card is valid. (???) Anyway, the Reference Manual statesthe following:     When a FIFO overrun or underrun condition occurs, the data are not lost because the peripheral request is not acknowledged by the stream until the overrun or underrun condition is cleared. If this acknowledge takes too much time, the peripheral itself may detect an overrun or underrun condition of its internal buffer and data might be lost. and If the DMEIFx or the FEIFx flag is set due to an overrun or underrun condition, the faulty stream is not automatically disabled and it is up to the software to disable or not the stream by resetting the EN bit in the DMA_SxCR register. This is because there is no data loss when this kind of errors occur. I don't know what to make of this exactly, but things seem to work fine.

[Tesla DeLorean]

Posted on August 27, 2014 at 22:44

One of the things to watch with an SDIO Write is that the DMA completes significantly before the SDIO's FIFO clears (think 128 bytes, 32 words)