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SCB_AIRCR behaves unpredictably

ajmeyer
Associate
Posted on November 15, 2009 at 15:59

SCB_AIRCR behaves unpredictably

3 REPLIES 3
ajmeyer
Associate
Posted on May 17, 2011 at 13:30

Per the cortex-m3 manual writing:

0x05FA0004->SCB_AIRCR engages a request for reset to all system peripherals. (Write 1 to SYSRESETREQ)

In an implementation of the usb dfu, we branch to user code from thread mode almost immediately after reset. In addition, handler mode logic in the USB LP_IRQ may update user code and engage a system reset so that the system branches to the new code.

The following code (runs as handler inside of USB_LP_IRQ) occasionally does the right thing:

*(SCB_AIRCR) = (u32)0x05FA004;

while (1) {

/* should never get here */

asm volatile(''nop'');

}

However, this does not consistently cause a reset, and the program often hangs inside of the inf. loop. I would just assume reset via AIRCR doesnt actually reset the PC and MSP, however this exact code HAS worked in the past.

What does ''request system reset'' actually mean? can it fail? How can we create a software reset with equivalent effect of pulling the reset line?

Is it possible to manually clear ourselves from handler mode, reset the PC and SP to the reset handler (pointed at 0x0800004), and reset any peripherals/exceptions such that we are very explicitly resetting the cortex without relying on flaky functionality from AIRCR?

We have had some promising results by setting the VECTRESET bit (0) of AIRCR, however technically this bit is ''reserved'' and not intended for application use. Whats the story on this bit?

Any and all input appreciated. Official response as to the exact functionality of SYSRESETREQ in AIRCR also desired. Thanks!

16-32micros
Associate III
Posted on May 17, 2011 at 13:30

Hi,

You can refer to our Cortex-M3 programming Manual PM0056 :

http://www.st.com/stonline/products/literature/pm/15491.pdf

for more details about these bits.

Note that this behavior is not the same as Hardware reset because it will not reset Debug Part. Ensure that your JTAG probes ( Ulink, J-link, R-link etc..) are not connected to your board when performing this reset.

You can also use hardware reset using internal watchdogs.

Cheers,

STOne-32.

tomas23
Associate II
Posted on May 17, 2011 at 13:30

Hello STOne-32,

what's the difference in the VECTRESET implementation between STM32 and generic Cortex-M3?

In the ARM TRM the VECTRESET is described as System Reset bit.

I suggest to write SCB_AIRCR = 0x05FA0007 (all reset bits active at the same time), huh?