Running stm32f407 DCMI interface with maximum frequency
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‎2015-05-24 7:24 AM
Posted on May 24, 2015 at 16:24
Hello
For some purpose i need to run DCMI interface with maximum frequency(it is 54MHz, right?), i provided pixclk pin with 56MHz clock(sysclock divided by 3 coming out of mco2 pin) but it seems that overrun occurs on DCMI fifo.What is the maximum applicable frequency of this interface and how can it be generated?Thanks.
4 REPLIES 4
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‎2015-05-24 9:51 AM
Posted on May 24, 2015 at 18:51
There's a 54 MHz, and a ratio limit against the AHB
Use an external generator. Use the I2S PLL and feed that out of MCO2 ?
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‎2015-05-24 10:17 AM
Posted on May 24, 2015 at 19:17
What would be the I2S PLL configuration?
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‎2015-05-24 12:27 PM
Posted on May 24, 2015 at 21:27
Some obvious factors for the PLL would be
#define PLLI2S_N 432 #define PLLI2S_R 8 #define PLLI2S_N 324 #define PLLI2S_R 6
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‎2015-05-24 7:19 PM
Posted on May 25, 2015 at 04:19
I use stm32f4discovery, it has on board 8MHz crystal.
According to page 226 of RM0090, it is recommended to set PLLM to 2 (8MHz crystal assumption) to minimize PLL jitter and according to page 264, PLLI2SR can't be larger than 7, so i think below is some proper configuration:PLLI2SN = 324PLLI2SR = 6This gives 108MHz clock for I2S and applying a division by 2, will give 54MHz on mco2 pin.