I've successfully set up an evaluation project on the STM32U5A9J-DK PCB with a custom 640x480 MIPI/DSI display in video mode. I've also configured the HexaSPI PSRAM in memory-mapped mode at 160MHz, which I've verified with a scope. My memory tests have all passed, and I've set up the display with double buffering and an RGB888 color scheme. Drawing to the frame buffer works as expected.
However, after porting the Embedded Wizard graphic library with CPU2D support, I'm experiencing graphical artifacts during heavy memory traffic. It appears that I'm hitting a memory bottleneck with three bus masters accessing the frame buffer and dynamic memory block in the external HexaSPI PSRAM.
Optimization Attempts
I've read AN4861 and attempted to optimize the frame buffer line length to be a multiple of 64, but this hasn't resolved the issue with CPU2D.
Questions
- Has anyone successfully run a display with these specs (640x480 RGB888, MIPI/DSI, HexaSPI PSRAM) at a frame rate >10 Hz on the STM32U5 series?
- I calculated the memory required LTDC bandwith [bit/s] the following: FrameRate * 640 * 480 * 3 * 8 = 147 Mbit/s @ 20 fps. It this correct?
- I read on the ST webpage the HSPI memory bandwith it up to 1 Gbit/s. I expect this to be true on the H7 series but not on the U5. What is the limit on the U5 series in memory mapped mode?
- Do I need to configure frame buffer pixel the line offset for the CPU2D peripheral as well?
