jlink fails to connect to stm32n6

[robojan]

Hey All,

I hope you can help me. I'm trying to bring up my new board, which contains a STM32N657IO. Attached are the schematics. You can assume the 5V supply is working(it is after a few bodge wires). 

My problem is as follows. I'm trying to connect to the STM32N6 over SWD using a JLink. It seems the SWD communication with the Debug port is successful, but the communication with the core fails. I get the following output when trying to connect to the MCU:

Device "STM32N657I0" selected.


Connecting to target via SWD
ConfigTargetSettings() start
---Setting ETM Base Address---
---Setting TF Base Address---
---Setting ETF Base Address---
---Setting TPIU Base Address---
ConfigTargetSettings() end - Took 24us
InitTarget() start
SWD selected. Executing JTAG -> SWD switching sequence.
DAP initialized successfully.
Can not attach to CPU. Trying connect under reset.
SWD selected. Executing JTAG -> SWD switching sequence.
DAP initialized successfully.
Connecting to CPU via connect under reset failed.
InitTarget() end - Took 104ms
Connect failed. Resetting via Reset pin and trying again.
ConfigTargetSettings() start
---Setting ETM Base Address---
---Setting TF Base Address---
---Setting ETF Base Address---
---Setting TPIU Base Address---
ConfigTargetSettings() end - Took 23us
InitTarget() start
SWD selected. Executing JTAG -> SWD switching sequence.
DAP initialized successfully.
Can not attach to CPU. Trying connect under reset.
SWD selected. Executing JTAG -> SWD switching sequence.
DAP initialized successfully.
Connecting to CPU via connect under reset failed.
InitTarget() end - Took 104ms
Error occurred: Could not connect to the target device.
For troubleshooting steps visit: https://wiki.segger.com/J-Link_Troubleshooting

I already investigated the following:

• 1.8V is present
• the 24MHz oscillator is running
• the 0.8V internal SMPS is running and producing 0.8V
• the reset line is high, and the jlink toggles it low while trying to connect
• I used an logic analyzer on the SWD lines, and I can see correct communication until the moment it tries to an R APc followed by an RDBUFF, which is responded with fault.
• Boot0 low or high, doesn't seem to matter
• I tried to connect via the USB ROM bootloader. The host detects an device, but the device never responds to the hosts set address request. (Only host to device communication, no reply)
• I don't see any activity on PG10, which may container bootloader debug output
• I tried to use STMCubeProgrammer, but It doesnt support the STM32N6 using the JLink
• I noticed that I forgot to tie PDR_ON to 1.8V, luckily this ball is in the corner of the chip so I could solder an wire to the ball (thin wire, lots of flux, and heating the wire to melt the solder of the ball to the wire over a small distance, connection seems solid)

These are my remaining ideas:

• Maybe the JLink doesn't support this new MCU correctly. I could buy an ST-Link v3minie
• Something is wrong with my power rails, maybe sequence.

So, my question is. Does anyone have an idea what could be wrong?

[RomainR. · Accepted solution]

Hi @robojan 

To be able to connect using STLink or J-LINK in JTAG/SWD, the STM32N6 must be in DEV_BOOT mode.
You must apply the correct level on BOOT1 (PA6) and BOOT0)
In the schematic, BOOT0=GND, but BOOT1 is floating/unconnected. I think the MCU is in unknow state.

Refer to the AN5967: in section 10 Boot configuration
https://www.st.com/resource/en/application_note/an5967-getting-started-with-hardware-development-for-stm32n6-mcus-stmicroelectronics.pdf

Refer also to my answer in the following post which can be also help.

https://community.st.com/t5/stm32cubeide-mcus/stm32-n657x0-q-code-generation-is-not-working/td-p/809494/highlight/true

Best regards,
Romain,

[robojan]

Hey Romain,

Thanks for you pointer. For some reason I had it in my head that as long as boot0 was defined, boot1 could be an don't care. (with the correct fuses). The dev-mode is still new to me. 

Sadly, I did not connect this ball to an external trace. Luckily with some effort I could drill a hole through the PCB and connect boot1 to 1.8V. Now I am able to connect with the J-Link. 

Device "STM32N657I0" selected.


Connecting to target via SWD
ConfigTargetSettings() start
---Setting ETM Base Address---
---Setting TF Base Address---
---Setting ETF Base Address---
---Setting TPIU Base Address---
ConfigTargetSettings() end - Took 35us
InitTarget() start
SWD selected. Executing JTAG -> SWD switching sequence.
DAP initialized successfully.
InitTarget() end - Took 6.93ms
Found SW-DP with ID 0x6BA02477
DPIDR: 0x6BA02477
CoreSight SoC-400 or earlier
Scanning AP map to find all available APs
AP[3]: Stopped AP scan as end of AP map has been reached
AP[0]: APB-AP (IDR: 0x54770002, ADDR: 0x00000000)
AP[1]: AHB-AP (IDR: 0x84770001, ADDR: 0x01000000)
AP[2]: AXI-AP (IDR: 0x44770004, ADDR: 0x02000000)
Iterating through AP map to find AHB-AP to use
AP[0]: Skipped. Not an AHB-AP
AP[1]: Core found
AP[1]: AHB-AP ROM base: 0xE00FE000
CPUID register: 0x411FD221. Implementer code: 0x41 (ARM)
Feature set: Mainline
Cache: L1 I/D-cache present
Found Cortex-M55 r1p1, Little endian.
Cortex-M (ARMv8-M and later): The connected J-Link (S/N xxxxxxxx) uses an old firmware module that does not handle I/D-cache correctly. Proper debugging functionality cannot be guaranteed if cache is enabled
FPUnit: 8 code (BP) slots and 0 literal slots
Security extension: implemented
Secure debug: enabled
PACBTI extension: not implemented
CoreSight components:
ROMTbl[0] @ E00FE000
[0][0]: E00FF000 CID B105100D PID 000BB4D2 ROM Table
ROMTbl[1] @ E00FF000
[1][0]: E000E000 CID B105900D PID 000BBD22 DEVARCH 47702A04 DEVTYPE 00 ???
[1][1]: E0001000 CID B105900D PID 000BBD22 DEVARCH 47711A02 DEVTYPE 00 DWT
[1][2]: E0002000 CID B105900D PID 000BBD22 DEVARCH 47701A03 DEVTYPE 00 FPB
[1][3]: E0000000 CID B105900D PID 000BBD22 DEVARCH 47701A01 DEVTYPE 43 ITM
[1][5]: E0041000 CID B105900D PID 004BBD22 DEVARCH 47754A13 DEVTYPE 13 ETM
[1][6]: E0003000 CID B105900D PID 000BBD22 DEVARCH 47700A06 DEVTYPE 16 ???
[1][7]: E0042000 CID B105900D PID 000BBD22 DEVARCH 47701A14 DEVTYPE 14 CSS600-CTI
[0][1]: E0080000 CID B105100D PID 001A0486 ROM Table
ROMTbl[1] @ E0080000
[1][0]: E0081000 CID B105900D PID 003BB908 DEVARCH 00000000 DEVTYPE 12 CSTF
[1][1]: E0082000 CID B105900D PID 001BB961 DEVARCH 00000000 DEVTYPE 32 TMC
[1][2]: E0083000 CID B105900D PID 001BB961 DEVARCH 00000000 DEVTYPE 21 TMC
[1][3]: E0084000 CID B105900D PID 005BB912 DEVARCH 00000000 DEVTYPE 11 TPIU
[1][4]: E0085000 CID B105900D PID 002BB909 DEVARCH 00000000 DEVTYPE 22 ATBR (?)
[1][5]: E0086000 CID B105F00D PID 001BB101 TSG
[1][6]: E0087000 CID B105900D PID 001BB963 DEVARCH 47710A63 DEVTYPE 63 STM
[1][7]: E0088000 CID B105900D PID 005BB906 DEVARCH 00000000 DEVTYPE 14 CTI (?)
[1][8]: E0089000 CID B105900D PID 005BB906 DEVARCH 00000000 DEVTYPE 14 CTI (?)
[1][9]: E008A000 CID B105900D PID 002BB914 DEVARCH 00000000 DEVTYPE 11 TPIU
I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way
D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
Memory zones:
  Zone: "Default" Description: Default access mode
Cortex-M55 identified.

Lets write some software! and hope that the warning about the caches will not be too much of an issue.