RTC of STM32L072CZ. DBP=1 needed, to write to RTC->ISR?

Only bits 8..13 of RTC->ISR are exception to the RTC write protection (0xCA 0x53 rule) and all RTC registers are in the backup domain so writing to them is subject to DBP=1.

JW

You are right. Thank you.

So, to put it clearly, even to just read the RTC calendar (time and date -and in that order, to guarantee consistency with each other-) the right way (doing repeated readings, until the two last ones match), the DBP=1 rule and the 0xCA 0x53 sequence rule must both be done. That is because, to do repeated readings, I need to write to RTC_ISR_RSF (to set it to 0, and then wait until it is 1 again, before doing the following reading), which is bit 5 in RTC->ISR, and bit 5 is no exception to the 0xCA 0x53 rule. And, since any write to any RTC register needs DBP=1, that is also needed. So, that is quite a long code, just to read the time and date.

> to do repeated readings, I need to write to RTC_ISR_RSF (to set it to 0, and then wait until it is 1 again, before doing the following reading),

You don't need to do that, except after INIT having been set/cleared, or similar quite exceptional cases. Otherwise, yes, you might read 2 cycles old information, but do you really care that much?

Additionally, note that the BYPSHAD locking mechanism may be ineffective. While the errata for your chip don't mention that, they are rather old too, and this flaw started to appear in errata in late 2016 (see. eg. the 'F407 errata).

So at the end of the day, you may be better off simply setting BYPSHAD=1 where the copying mechanism indicated by RSF is simply bypassed, and if you need it, ensure consistency by reading the time/date registers twice, repeating until they match.

JW