2017-01-18 12:45 AM
Hi,
is it ensured that there is just one bit set in the RCC_CSR register when it is cleared and afterwards a certain reset occurs? Or is there a case so that more than one reset reason bit becomes set?
There is no statement in the reference manual about this.
Thank you
2017-01-18 08:04 AM
Hello
Neumann.Sascha
,It's possible in case of
internal reset
to have2 Flag set
in the same time.
Regards
Imen
2017-01-18 08:31 AM
Which chips?
I tend to prioritize and clear the bits I'm looking for, ie specifically look for Standby or Watchdog type flagging over button