Reference pierce oscillator design available for STM32G0B1x?

[RHube.3]

I'm developing a new design with a STM32G0B1x uC. Therefore, I will use a 12MHz or 8Mhz external (HSE) crystal quartz from Abracon. I just read through the AN2867 and did some calculations. Now I'm at the point where I would need to measure the drive level. Do I need an external Resistor to limit the current through the crystal or not?! If yes, the calculated gm critial (with the calculated Rext) would be over the defined gm critical max. limit of the STM32 datasheet and therefore I would have to use another crystal with different load capacitors/frequency..

As this measurement is not too easy, I'm curious if there are not some reference designs for my problem? I found a nucelo board with a 8MHz NX3225DG crystal, but this is hard to buy component.

I was just at the electronica and an epson crystals employee told me, that this external resistor is no longer necessary as this uC is a low power device and the internal pierce oscillator unit will not have the power to destroy the external crystal! What are your experiences or solutions?

[Peter BENSCH]

Welcome, @RHube.3​, to the community!

If you list the crystal types in question or give the necessary crystal parameters (f, Rs, C0, CL), a quick check can be made.

In general, it can be said that a measurement of the drive level is mentioned in AN2867, but is not absolutely necessary. As a rule of thumb, the calculated load capacitors are quite sufficient. However, the layout is extremely important, for which very helpful hints are given in AN2867. There have also been several threads here in the community that have dealt with this topic, e.g. here.

In addition, I'd like to mention that the gain margin is particularly easy and stable to fulfil when a crystal with a lower frequency <10MHz is connected to HSE. This is also one of the reasons why a frequency of 8MHz was chosen in STMicroelectronics' development boards, e.g. the NUCLEO.

Regards

/Peter

[RHube.3]

Hi Peter,

Thanks for your super fast answer 🙂 I don't know if I'm aloud to post a full part name here, so it's a Ceramic base SMD Crystal, Operating Mode Fundamental.

f = 12MHz

Rs (ESR) = 100Ohm

C0 = 2pF

CL = 8pF

my calculated Load capacitor value = 6pF (with 5pF stray capacitance for calculation)

In the nucleo design is a 8MHz crystal, but there is a 100Ohm resistors in each line from the crystal to the uC?

[Peter BENSCH]

If it is not forbidden by your company, you may of course mention the part number of the crystal. But the parameters are quite sufficient and after calculating them I have determined for your STM32G0B1:

• gm(crit) = 0.227mA/V
• gm(min) = 7.5mA/V
• margin = 32.982

Due to the low Rs, the margin is well above the minimum of 5, which is completely sufficient and you can use the crystal without any problems.

Normally, only zero-ohm resistors are used as jumpers in the NUCLEO.

The 100ohm resistors between the OSC pins and the crystal in the MB1360 rev C02, which is used for the STM32G0x, are not populated anyway and are only placeholders. The corresponding UM2324 also refers to AN2867 for component selection for the HSE, so the 100 ohms of R33/34 are not to be regarded as a mandatory value.

If the problem is solved, please mark this thread as answered by selecting Select as best, as also explained here. This will help other users find that answer faster.

Regards

/Peter

[RHube.3]

ok, great. the 0.227mA/V is what I expected. In the datasheet is only mentioned Gm (Maximum critical crystal transconductance) which I assumed to be Gm_crit_max. The value is 1.5mA/V. There is a note "Startup", so this value is only to be considered at startup?

Where did you get the value 7.5mA/V as gm(min)?

The App. Note 2867 defines "If Gm_crit_max is specified instead, make sure that gmcrit for the oscillation loop is smaller than the specified Gm_crit_max value". So I went for:

gmcirt calculated = 0.227mA/V --> 0.227mA/V< 1.5mA/V and therefore this crystal should work.

kind regards,

Roger

[Peter BENSCH]

You will find the value for gm(min) at HSE in AN2867, table 6 as part of the block with:

STM32L4, STM32L4+, STM32L5, STM32H7, STM32G0, STM32G4 and STM32MP1

But please don't forget to layout GND accordingly, i.e. shaped like a (GND) hand holding a stone (crystal), where the "hand" must be separated from the rest of the GND layer and only connected via the "arm" to the closest GND pin of the STM32, see AN2867, section 7.2, fig. 14...16. I hope that the linguistic picture illustrates this in an understandable way? 😊

Good luck!

/Peter