Real breakpoints with ADC and interesting phenomenon

[Zheng Liang]

Posted on August 08, 2017 at 14:52

I'm using STM32F103CB to convert the analog outputs from three polar hall sensors arranged circularly, a magnetic actuator rotates in the center, but I get the voltage value with strange breakpoints, and these happened with a interesting phenomenon which happens with a phase at voltage value of 2048  and I can't explain why, maybe someone had faced this problem, please help and tell me how to solve this.

Problem phenomenon: the value from ADC channel will have a breakpoint when it or other ADC channels in ADC channel group at voltage 2048, here are the screenprint with brief:

1. Single channel reading:
2. Tow phases with 60

   � space?

   

3. Tow phases with 120

   � space?

   

4. Three phases with 60

   � space:

   

What I tried to solve this:

1. disable DMA
2. change the hall sensor output voltage amplitude
3. replaced three F103 chips
4. changed the rank of ADC channel times
5. disable ADC2 and only use ADC1
6. disable ADC1 and only use ADC2
7. dual ADC mode
8. add more delay in converted interruption

but nothing changed

:(

If you have some suggestions, please let me know

Thanks,

Zheng

#adc-reads #adc-config #hall-sensors #f103-adc-dma

[Vangelis Fortounas]

Posted on August 08, 2017 at 15:17

Hello!

Did you check the real values to confirm the breakpoints?

There is some posibility, theese breakpoints caused by your logic analyser.

Post some code you use to take the values.

[Tomas DRESLER · Accepted solution]

Posted on August 08, 2017 at 16:25

Hi Zheng,

do you have long enough sampling time for ADC inputs, according to source impedance? Further please avoid capacitors at ADC inputs.

[Zheng Liang]

Posted on August 08, 2017 at 18:39

HiVangelis,

Thanks for your reply, these data were not shownin logic analyser, it's the real values flow transfered from MCU by serial port and 485 to computer, and visualized by python, I think the problem is like

dresler.tomas

‌ said, wrong impedance with sampling time.

[Zheng Liang]

Posted on August 08, 2017 at 18:51

Hi Edison,

Thank you, I checked my configuration after read your reply, the impedance of the source was higher than the calculated max impedance base on my sampling time setting, longer the sampling time solves the problem temporarily, I will reduce the impedance of source in next step. 

I don't get why avoid capacitors at ADC inputs? I have placed 2nF capacitors near each the ADC pin for low-pass filter

[Tomas DRESLER]

Posted on August 09, 2017 at 09:11

Because internal sampling capacitor is part of the ADC structure and gets charged to Vref+/2. During sampling phase, the charge may influence your low-pass capacitor voltage, and if it is not restored by low impedance source during conversion time, the voltage may travel.