2017-03-02 10:00 PM
I am using ADC with DMA on STM32L051. Conversion time is 50us (20 000 conv. per second). When I read RTC-registers (RTC_SSR, RTC_TR, RTC_DR) sometimes the CPU freezes for approx. 113 us causing ADC overrun and loss of one conversion result (113 us > 50 us * 2).
I have found the only way to solve this problem:
1) Put RTC read commands inside of interrupt handler.
2) Read only one RTC-register at a time.
I am completely unsatisfied by this solution. Is there any better way to read RTC-registers without ADC result loss?
Conditions:
1) CPU:
STM32L051R8T6
2) System clock is 1.048 MHz (MSI).
3) AHB and APB2 clocks are the same, APB1 clock is
1.048/4 MHz.
4) RTC clock source is external 32.768 kHz crystal.
5) ADC sequence (2 conversions) started by TIM6, DMA-interrupt after 100 conversions is used.
Thanks for any help!
2017-03-02 11:44 PM
You mean that one sample is 'skipped', i.e. literally missing from the DMA buffer?
Or that the processor doesn't succeed to read from a circularly-filled DMA buffer fast enough and the buffer gets overwritten by DMA while you read?
JW
2017-03-03 12:22 AM
I mean that one sample is skipped. ADC overrun bit is set by hardware. This skip matches reading RTC-registers.
2017-03-06 06:47 AM
How exactly are you reading the RTC? Post code.
JW
2017-03-06 10:04 PM
int RTC_SSR, RTC_TR, RTC_DR;
...
...
RTC_SSR = RTC -> SSR;
RTC_TR = RTC -> TR;RTC_DR = RTC -> DR;2017-05-05 12:20 PM
Seems like you may saturate the AHB bus. The DMA accessing ADC requires ~10 cycles to complete one transfer, which means 10 us, reading one RTC register takes 8-12 clocks (8-12 us) each, entry and exit from interrupt takes 32 cycles with full bus load (32 us). Does the overrun happen at the time of some interrupt or immediately/randomly? Can you test with IRQs disabled?
I'd try two things primarily:
RTC: BYPSHAD=0
APB1 prescaler=1 or 2, to increase throughput to RTC
2017-05-06 06:22 AM
Another easy thing to test would be to increase MSI speed.
2017-05-06 06:42 AM
@Edison: Yous state number of cycles of the DMA transfer. Are these number public documented or only insider knowledge?
2017-05-06 01:09 PM
Uwe,
while L0 is not listed there, I believe AN2548 pertains to L0's DMA too.
JW