I am working on an old code written by someone. The application requires reading 13 ADC channels roughly at 8k samples per second. The read values are written in two buffers in double buffer mode (4096 each).
The ADC is implemented in scan mode with the sequence of channels in ADC_SQRx registers. ADC is configured in 12 bit mode. ADC conversion is triggered by rising edge of timer2 channel 2 set at a ~8Khz frequency.
DMA is configured as peripheral to memory transfer in double buffer mode, with DMA2 Stream0 which can take ADC1 as source.The NDTR register in DMA is written with a value of 4082 (multiple of 13 channels). DMA stream threshold is set as half full.
I think there is data corruption in buffer and I am trying to understand the cause.
The reference manual says the NDTR values get decremented after each transaction. What is meaning of transaction here? Is it each data transfer from FIFO to memory address?
Example: If I am reading 13 channels (half word each) and FIFO threshold is set at half full ( FIFO size of 4 words(8 half words);4 half words when FIFO is half full). When the first
FIFO to memory transaction happen, data of first four channels will be transferred to memory and NDTR will be decremented. To transfer one set of data for 13 channels (13 half words) atleast four transaction should happen, which means NDTR will be decremented by 4 steps. Is this understanding correct?
Since there is only one ADC data register do we not have to configure the EOCS bit so as to trigger a DMA request after each channel conversion complete, instead of after each sequence of channel conversion complete. The way this section is described in reference manual is that you can have either settings of EOCS in scan mode.
How does the controller avoid over writing of data in data register if DMA interrupt triggers will happen only at the end of sequence conversion ?
