2017-10-28 09:54 AM
Hello engineers,
could someone help me with one issue? Iam finding way to read output state of timer but unsuccessfull. I have one timer triggered by Comparator. This timer is configured as one pulse and is master for another timer which is configured in gated mode. Any advice for reading state of one pulse timer?
Many thanks
2017-10-28 11:27 AM
Hello,
Yo can simply enable CCR interrupt in one pulse Timer. In the corresponding CallBack you increment a variable. This variable will show you how much the Timer output state has changed.
2017-10-28 11:54 AM
The physical pin is readable via GPIOx->IDR, I'd expect it would work as an EXTI input regardless of the peripheral assignment. The Internal status of the TIM can be seen via the SR, CNT, and CCRx registers.
2017-10-28 02:38 PM
Hello,
Arent those registers just for settings?
2017-10-28 02:50 PM
No, not exactly. Status will reflect things, I'd expect CCx to signal in SR, I'd expect CNT to reflect current phase, and CCRx on the indirect channel to be usable to latch things. You'd likely need to experiment to get the info you're looking for, but I think the hardware should be able to report things you can use.
2017-10-29 09:11 AM
Hello Clive,
The SR is only status register of interrupt flags. To clarification i will describe my problem.
I have ADC REG channel triggered by TIM15. Tim15 is slave in trigger mode and TIM16 is master. TIM16 is one pulse timer. But i have also INJ channels which i want to use measure significant datas(temperature,voltage,current). INJ channels cannot be used for DMA thus i used REG channel for major measurement. when REG channel is not active (the TIM16 is in 0) i need to measure INJ channels continuously. That is why i cannot use edges for detecting. INJ cannels are started by sw from main while loop. and i need to check before every sw start of INJ channels if timers output is in 0 or 1.
Please help me.
2017-10-29 01:30 PM
I don't understand why do you need this, but if you trigger an interrupt upon compare and update, you can keep simulate the state of output in software - this is basically the same as Omar said above.
JW