I'm working with a 24-bit external ADC (LTC2512-24) and stm32u5 (NUCLEO).
With the MCU as master, after Data Ready Line (DRL) falling edge from the ADC I need to read 24bits via SPI within 740ns and then have SCK remain quiet until the next DRL falling edge (the quiet is to prevent causing ADC noise).
I have used autonomous mode triggered on DRL falling edge and this works to generate a DMA request and read a sample value, but it only triggers once and reads one ADC sample.
To get it to read in a cycle I have to use the SPI transfer complete ISR to setup a new DMA receive transfer but this means I have to process each sample individually which means I need to wake very frequently. How can I read more samples in one transfer without continuous SCK output?
Could I use DRL to trigger a one-pulse mode timer output with a width equivalent to 24 SCK pulses and use this as my RDY signal for SPI? When RDY is low won't this pause the transfer, so I could then use a large TSIZE to receive many samples?
Is there an easier/better method?
