You're missing several steps from the 'L4 ADC initialization. Instead of talking about them, here's a portion of code from where you can identify them:
// let's choose the ADC clock derived from ADC's AHB interface (AHB2), rather than independent clock from RCC - no need to prescale, ADC can go as high as current Range (voltage regulator) setting allows the sysclk to go
ADC123_COMMON->CCR = 0
OR (0b01 * ADC_CCR_CKMODE_0) // 01: HCLK/1 (Synchronous clock mode). This configuration must be enabled only if the AHB clock prescaler is set to 1 [...]
;
/*
To start ADC operations, it is first needed to exit Deep-power-down mode by setting bit DEEPPWD=0.
Then, it is mandatory to enable the ADC internal voltage regulator by setting the bit
ADVREGEN=1 into ADCx_CR register. The software must wait for the startup time of the
ADC voltage regulator (T ADCVREG_STUP ) before launching a calibration or enabling the
ADC. This delay must be implemented by software
*/
ADC1->CR = 0
OR (0 * ADC_CR_DEEPPWD)
OR (1 * ADC_CR_ADVREGEN)
;
LoopDelay(100); // t ADCVREG_STUP = 20us max -- this is uncalibrated delay, but it's certainly more than 1 cycle per loop, so at 4MHz this is at least 100/4=25us
// we are not going to be measuring differentially so don't need to set ADCALDIF prior to launching calibration
ADC1->CR = 0
OR (1 * ADC_CR_ADVREGEN)
OR (1 * ADC_CR_ADCAL)
;
while (ADC1->CR AND ADC_CR_ADCAL); // wait until calibration ends
// and that's it
// ADEN bit cannot be set during ADCAL=1 and 4 ADC clock cycle after the ADCAL bit is cleared by hardware (end of the calibration), so let's waste some time by setting up the conversion
// in 'L476, there's a nice gotcha in the form of additional analog switch in GPIO
GPIOA->ASCR = 0
OR GPIO_ASCR_ASC1
OR GPIO_ASCR_ASC2
;
Note, that leaving clock at default in ADC_CCR.CKMODE leaves it at 00: CK_ADCx (x=123) (Asynchronous clock mode), generated at product level , and that is set in RCC_CCIPR.ADCSEL which is by default at 00: No clock selected. Note also the GPIOx_ASCR switch gotcha,, which is unique to the mid-range 'L4.
JW
