2017-08-17 12:15 PM
Hi,
has anyone checked in the stm32f4xx.h Lib the RCC_CFGR_MCOxPRE Register?
The values mentioned in the RM0090 manual don't fit the stm32f4xx.h
stm32f4xx.h:
&sharpdefine RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
&sharpdefine RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)&sharpdefine RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)&sharpdefine RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)&sharpdefine RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)&sharpdefine RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)&sharpdefine RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)&sharpdefine RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)Manual RM0090:
Bits 27:29 MCO2PRE: MCO2 prescaler
Set and cleared by software to configure the prescaler of the MCO2. Modification of thisprescaler may generate glitches on MCO2. It is highly recommended to change thisprescaler only after reset before enabling the external oscillators and the PLLs.0xx: no division100: division by 2101: division by 3110: division by 4111: division by 5Bits 24:26 MCO1PRE: MCO1 prescalerSet and cleared by software to configure the prescaler of the MCO1. Modification of thisprescaler may generate glitches on MCO1. It is highly recommended to change thisprescaler only after reset before enabling the external oscillators and the PLL.0xx: no division100: division by 2101: division by 3110: division by 4111: division by 5Bit 23 I2SSRC: I2S clock selectionCan anyone verify this, or I'm just mixing something up?
Thanks
#stm32f4xx.h #stm32f4 #register #errorSolved! Go to Solution.
2017-08-17 02:46 PM
,
,
I might do this
♯ define RCC_CFGR_MCO2PRE_DIV5 (RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
2017-08-17 12:45 PM
>> I'm just mixing something up?
The define describe bit positions, not numeric values from the table
ie MCO2 setting of 5 would be
RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2 // 111 = DIV5
2017-08-17 02:10 PM
Thanks Clive,
ya superb!
2017-08-17 02:46 PM
,
,
I might do this
♯ define RCC_CFGR_MCO2PRE_DIV5 (RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)