bypass config with STDPERIPH_DRIVER

[mahmoud boroumand]

Posted on August 17, 2017 at 13:05

hello 

i use stm32f030f4 and use 10MHz oscillator (BYPASS) and i want achieve to 48mhz in mcu.

and i use STDPERIPH_DRIVER and keil v5.what configuration i have to do ?what code i have to add to my project?

[Tesla DeLorean]

Posted on August 17, 2017 at 13:38

You'd need to modify the clock/pll setting code in system_stm32f0xx.c

Not sure the available multiplier and divider settings will get you from 10 MHz to 48 MHz, review the setting options in the reference manual.

[mahmoud boroumand]

Posted on August 17, 2017 at 13:52

If i want get 10MHz to 10 mhz what code i have to add?

i dont know how enable bypass.

[RomainR.]

Posted on August 17, 2017 at 17:49

Hi,

HSE 10MHz input frequency does not allow you to get the 48MHz SYSCLK with PLL.

HSE PREDIV is between 1 and 16PLLMul is between 2 and 16

But you can with a HSE frequncy of 8MHz or 12MHz

For 8Mhz PLL Input:

HSE_PREDIV = 1PLL_MUL = 6

For 12Mhz PLL Input:

HSE_PREDIV = 1PLL_MUL = 4

BR

[Tesla DeLorean · Accepted solution]

Posted on August 17, 2017 at 19:00

RCC_HSEConfig(RCC_HSE_ON); becomes RCC_HSEConfig(RCC_HSE_Bypass); and you don't need to wait for it to start

or something along these lines in system_stm32f0xx.c, called via SystemInit()

static void SetSysClock(void)

{

/******************************************************************************/

/*            HSE BYPASS used as System clock source                          *//******************************************************************************/

  /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/

  /* Enable HSE BYPASS */  RCC->CR |= ((uint32_t)RCC_CR_HSEBYP);

  /* Enable Prefetch Buffer and set Flash Latency */

  FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;

  /* HCLK = SYSCLK */

  RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;

  /* PCLK = HCLK */

  RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;

  /* Select HSE as system clock source */

  RCC->CFGR = (RCC->CFGR | (uint32_t)((uint32_t)~(RCC_CFGR_SW))) | (uint32_t)RCC_CFGR_SW_HSE;

  /* Wait till PLL is used as system clock source */

  while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_HSE);}