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Question about STM32 EXTI

icdiy
Associate II
Posted on December 17, 2013 at 06:46

Hi Sir,

I'd like to ask one question about STM32 EXIT.

If interrupt pin asserted during EXT_IMR is disabled, will the interrupt be recorded by EXTI_PR and intrrupt is issued to CPU core immediately after EXT_IMR re-enabled? Thanks.

12 REPLIES 12
icdiy
Associate II
Posted on December 21, 2013 at 01:17

Thanks. I tried to get the all errta from ST, but did find anything about my issue.

I think it is the document error f the below words are true:

''Did you disable the EXTI or did you mask it?

There is a big difference.

If you disable an IRQ - it can never trigger. If you mask it - it can trigger but the CPU has been set to ignore it.

Enable is done in the EXTI part of the IRQ controller.

Masking is done in the NVIC part of the IRQ controller..''

I write EXTI_IMR as 0, so I ''disable the interrupt'' and it can ever trigger. That can explain what I saw in the experiment.

But the figure 20 will mislead the readers think that EXTI_IMR only gate the interrupt request to CPU at the final stage, and the interrupt request will be recorded in EXTI_PR even if EXTI_IMR is 0 and an interrupt will be issued to CPU core after EXTI_IMR is programmed as 1. 

icdiy
Associate II
Posted on December 21, 2013 at 01:22

****Sorry that there is some typo in my last message, I repost it********

Thanks. I tried to get all the errta from ST, but did not find anything about my issue.

I think it is the document error if the below words from your last comment are true:

''Did you disable the EXTI or did you mask it?

There is a big difference.

If you disable an IRQ - it can never trigger. If you mask it - it can trigger but the CPU has been set to ignore it.

Enable is done in the EXTI part of the IRQ controller.

Masking is done in the NVIC part of the IRQ controller..''

I write EXTI_IMR as 0, so I ''disable the interrupt'' and it can ever trigger. That can explain what I saw in the experiment.

But the figure 20 will mislead the readers think that EXTI_IMR only gate the interrupt request to CPU at the final stage, and the interrupt request will be recorded in EXTI_PR even if EXTI_IMR is 0 and an interrupt will be issued to CPU core after EXTI_IMR is programmed as 1. 

chen
Associate II
Posted on December 23, 2013 at 11:23

Hi

Does this answer your original question?

Does it allow you to do what ever it was you wanted to do now?