Posted on February 18, 2018 at 18:16Hi,
I am using the Quad SPI peripheral of the
http://www.st.com/en/microcontrollers/stm32f767zi.html
.
After I played around with it and watched the signals with an logic analyzer and oscilloscope, I noticed something strange.
After the dummy cycles phase the
first nibble of the
first data byte gets on the data lines
with the rising clock edge.
But since I am in
SPI mode 0, the data lines should have the right state some time before the rising edge.
Thus there is a high chance that the first data nibble gets received corrupted by the slave.
After looking into the errata it became more clear whats going on.
However, the workaround is not really helpful.
The errata recommends to use the alternate byte phase instead of the dummy phase.
But the alternate byte phase drives the data lines to an specific state instead of high impedance used in the dummy cycle phase.
So there is an chance of hardware damage in case the master switches from transmitting to receiving mode and for a moment both trying to drive the data lines to an specific state.
Is there a better workaround?
Is there an alternative STM32 device with fully working Quad SPI?
I explained the problem with more details on
https://electronics.stackexchange.com/questions/356881/stm32f7-quad-spi-dummy-cycle-behavior
but I got no solutions so far.
#quadspi #spi
