QSPI write external flash memory STM32F746 Discovery Board
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‎2020-08-02 3:17 AM
Hello, I am using STM32F746 Discovery Board and want to write and read data to external flash memory . I gone through example code from STM. There is one function called QSPI_DummyCyclesCfg, I am not able to understand it completely.
/* Configure Volatile Configuration register (with new dummy cycles) */
QSPI_DummyCyclesCfg(&hqspi);
Here first we are trying to read READ VOLATILE CONFIGURATION REGISTER and doing below manipulation and writing back value in WRITE VOLATILE CONFIGURATION REGISTER.
MODIFY_REG(reg, 0xF0, (DUMMY_CLOCK_CYCLES_READ_QUAD << POSITION_VAL(0xF0)));
I am not able to understand reason for volatile register manipulation. Any suggestion.
static void QSPI_DummyCyclesCfg(QSPI_HandleTypeDef *hqspiH)
{
QSPI_CommandTypeDef sCommand;
uint8_t reg;
/* Read Volatile Configuration register --------------------------- */
sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE;
sCommand.Instruction = READ_VOL_CFG_REG_CMD;
sCommand.AddressMode = QSPI_ADDRESS_NONE;
sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
sCommand.DataMode = QSPI_DATA_1_LINE;
sCommand.DummyCycles = 0;
sCommand.DdrMode = QSPI_DDR_MODE_DISABLE;
sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
sCommand.NbData = 1;
if (HAL_QSPI_Command(&hqspi, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
{
Error_Handler();
}
if (HAL_QSPI_Receive(&hqspi, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
{
Error_Handler();
}
/* Enable write operations ---------------------------------------- */
QSPI_WriteEnable(&hqspi);
/* Write Volatile Configuration register (with new dummy cycles) -- */
sCommand.Instruction = WRITE_VOL_CFG_REG_CMD;
MODIFY_REG(reg, 0xF0, (DUMMY_CLOCK_CYCLES_READ_QUAD << POSITION_VAL(0xF0)));
if (HAL_QSPI_Command(&hqspi, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
{
Error_Handler();
}
if (HAL_QSPI_Transmit(&hqspi, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
{
Error_Handler();
}
}
Thanks
- Labels:
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QSPI
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STM32F7 Series
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‎2020-08-02 10:53 AM
>>I am not able to understand reason for volatile register manipulation. Any suggestion.
So the hardware and software has a consistent understanding of the settings/expectation, especially where those differ from the factory defaults for the memory IC.
Could be optimized if setting is already correct.
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‎2020-08-02 8:43 PM
OK, I will divide my question in below part :
- Why we are setting volatile register for non volatile memory (Flash) ? Why we care to set any volatile register ?
- What exactly we are looking to write back as settings?
I also checked datasheet but unable to get reason. Btw external flash memory is N25Q128.
Thanks
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‎2020-08-02 9:05 PM
Dummy cycles for read​ing allows the chip time to prefetch enough data to subsequently stream data at a given clock rate.
Buffering the data has time constraints which are not directly related to the clock you provide.​
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‎2020-08-02 9:19 PM
Sorry I am confused. Post transmit commands, we are waiting for status register in Auto Polling Mode. so why we need this dummy cycles. Can you please elaborate.
Order of code : Write Enable ->Sector Erase -> Polling Status ->Write Enable -> Program(write data to flash) -> Polling Status -> DummyCycles -> Read
Thanks
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‎2020-08-02 9:42 PM
The dummy cycles for read are like waits states. The STM32 and QSPI memory IC need to agree on the number of cycles before data will start to appear. This is programmed into a register in the memory device​, but is only a portion of the register and there requires a read, replacement of bits and rewriting.
​
The value is used for the 4-bit read mode, where the memory bandwidth will be maximized.
​
Sorry your confused​, not sure Im going to be able to resolve that.
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‎2020-08-02 10:41 PM
Okay, So In simple words its system delay to wait for read back data.
- Suppose If I am just want to write data to external Flash to multiple pages, I can do it without Dummy cycles, Correct?
- Rather than dummy cycles, I can put delay for like a mill seconds before read it back and during same time controller can do other task than wasting CPU cycles, Correct ?
Thanks
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‎2020-08-02 11:11 PM
no​
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‎2020-08-02 11:18 PM
than ?
