2022-02-28 12:55 PM
With the ICD I found that sometimes, between the MDMA IRQ Handler - where the QSPI TCIE bit is set, and the QUADSPI_IRQHandler, the TCIE bit is cleared.
But I haven't been able to determine where or how it is being cleared; I've eliminated all locations in code related to the QUADSPI->CR.
1) So the first question is why can't I see where the TCIE bit is being cleared? Or what exactly is doing it.
I recently discovered that my issue goes away by making the QUADSPI IRQ and MDMA IRQ the same priority, while making the MDMA sub priority higher (logically) than the QUADSPI IRQ.
Before: MDMA - priority 14, sub 0, QUADSPI - priority 15, sub 0
After: Both priority 14, MDMA sub 0, QUADSPI sub 1
2) Second question is how is this priority change solving the problem?
Solved! Go to Solution.
2022-02-28 01:51 PM
Watch that looking at peripheral registers in the debugger view can touch/change states, they are not memory but tied to other synchronous logic. Assume the debugger is invasive.
QSPI Flash typically can only write up to whole sectors, at sector aligned addresses. ie Micron parts writing 256 bytes at a time maximum.
2022-02-28 01:51 PM
Watch that looking at peripheral registers in the debugger view can touch/change states, they are not memory but tied to other synchronous logic. Assume the debugger is invasive.
QSPI Flash typically can only write up to whole sectors, at sector aligned addresses. ie Micron parts writing 256 bytes at a time maximum.