QSPI RAM on OSPI Interface of H7A3 MCU issues

[CBerg]

Hi Guys,

I need some help / input:

I am trying to get the communication running between my Nucleo H7A3 and a Shield with a ISSI QuadSPI RAM in a SOP-8 Package running.

Scenario:

I am debugging with my Scope, I have a digital Probe on all 6 lines (CSn, Clock and DIO0-3) and I can see the communication.

First issue:

I am sending the command "0x05 - read mode register". I can see the outgoing communication on the scope, I can see the incoming communication on the scope. I can see on the scope that the RAM is sending a response - with the default Mode Register Value. But the Variable I am reading ins, is not updated with that value.

My Code:

	OSPI_RegularCmdTypeDef cmd = {0};
	uint8_t buf[4] = {0,};

	cmd.Instruction				= SRAM_CMD_RDMR;							// instruction byte
	cmd.InstructionMode			= HAL_OSPI_INSTRUCTION_1_LINE;				// mode of the instruction
	cmd.InstructionSize			= HAL_OSPI_INSTRUCTION_8_BITS;				// size of the instruction

	cmd.DataMode				= HAL_OSPI_DATA_1_LINE;						// data mode: 1 Line
	cmd.NbData					= 1;										// number of data transfered with the command
	cmd.DummyCycles        		= 0x00;										// number of dummy cycles before data phase

	HAL_StatusTypeDef status;
	status = HAL_OSPI_Command(hSramOSPI, &cmd, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
	if(HAL_OK != status) {
		return(1);
	}

	status = HAL_OSPI_Receive(hSramOSPI, buf, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
	if (HAL_OK != status) {
		return(1);
	} else {
		SRAM_modereg = buf[0];
	}

I see literally in the scope 2 Bytes: 0x05 (=read Mode register command) and the response 0x40 - which is the default value of the chip according to its datasheet. But the buf variable, as well as the SRAM_modereg variable, where it is copied to remain 0.

I am using the MCU, the D-Cache and the I-Cache - Am I running in some weird Cache issues here - even if I am using OSPI in Blocking mode? Are there some DMA Transfers in the Background I am not aware of or something similar?

Second Issue:

If I use anything other than

cmd.AddressMode = HAL_OSPI_ADDRESS_NONE;

like 1 Line or 4 Lines for the address Phase, there is no communication at all on the bus. If I disable the Address phase, I can see communication on the both no matter which mode (SPI or QSPI) I am in. My Code:

static uint8_t rOS_SRAM_read(uint32_t addr, uint8_t * pData, uint32_t dataSz) {
	// @brief	read from SRAM in Quad-Mode (Blocking)
	// @PAram	u32 addr: address
	// @oaram	u8* data: read buffer pointer
	// @PAram	u32 dataSz: # of data to be read
	// @return	u8 status: 0 = OK (no error)

	if (pData && dataSz) {
		OSPI_RegularCmdTypeDef cmd = {0};
		cmd.Instruction				= SRAM_CMD_READ;							// instruction byte
		cmd.InstructionSize			= HAL_OSPI_INSTRUCTION_8_BITS;				// size of the instruction

		cmd.Address					= addr;										// data address
		cmd.AddressSize				= HAL_OSPI_ADDRESS_24_BITS;					// size of the address (typ. 24 bit)

		cmd.NbData					= dataSz;									// number of data transfered with the command

		if(SRAM_quad) {
			cmd.InstructionMode			= HAL_OSPI_INSTRUCTION_4_LINES;				// mode of the instruction
			#ifndef SRAM_NOADDR
			cmd.AddressMode				= HAL_OSPI_ADDRESS_4_LINES;					// send an address?
			#endif
			cmd.DataMode				= HAL_OSPI_DATA_4_LINES;					// data mode: send data or just command
			cmd.DummyCycles        		= 0x2;										// number of dummy cycles before data phase
		} else {
			cmd.InstructionMode			= HAL_OSPI_INSTRUCTION_1_LINE;				// mode of the instruction
			#ifndef SRAM_NOADDR
			cmd.AddressMode				= HAL_OSPI_ADDRESS_1_LINE;					// send an address?
			#endif
			cmd.DataMode				= HAL_OSPI_DATA_1_LINE;						// data mode: send data or just command
		}

		HAL_StatusTypeDef status;
		status = HAL_OSPI_Command(hSramOSPI, &cmd, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
		if(HAL_OK != status) {
			return(1);
		}

		status = HAL_OSPI_Receive(hSramOSPI, pData, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
		if (HAL_OK != status) {
			return(1);
		}
	}

	return(0);
}

No communication at all means: No Chip Select, No Clock, all data lines are idle in the Scope. The OSPI peripheral simply does nothing.

I have some experience with QSPI SRAM on an G4, but I am new to the OSPI Peripheral on the H7. Is there any major differences in the behavior of the QSPI functionality I am not aware of and therefore stumbling over? My approach was similar to that what I got successfully running on an G4, but I have absolutely no Idea why the H7 OSPI-Peripheral would simply do nothing at all, when I add an address phase!?

Any Help / input is appreciated! Thanks guys!