2013-04-24 04:33 AM
Hello everybody,
I ever look on webside if previous post treat my problem, but they not resolve my pb. The problem is, I try to pramreter the TIM1 PWM output on STM32, but it do not work. The TIM1 counter register CNT is counting realod, but it dosen't switch PA8. However the GPIOA IDR8 folow the overflow of CCR1. This is my code : GPIO_DeInit(GPIOA); RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA|RCC_APB2Periph_AFIO, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA|RCC_APB2Periph_AFIO, DISABLE); [...] // PWM output i=8; GPIO_StructInit(&GPIOA_InitStruct[i]); GPIOA_InitStruct[i].GPIO_Pin = GPIO_Pin_8; GPIOA_InitStruct[i].GPIO_Speed = GPIO_Speed_50MHz; GPIOA_InitStruct[i].GPIO_Mode = GPIO_Mode_AF_PP; // Alternate Fonction GPIO_Init(GPIOA,&GPIOA_InitStruct[i]); [...] RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); /* configures the timer 1 clock and divisors */ TIM_DeInit(TIM1); TIM_1.TIM_Prescaler = 550 ; //550 => 1sec // 36000000/9= 4 Mhz => periodes de 0.25µs TIM_1.TIM_Period = 65535 ; //400 TIM_1.TIM_ClockDivision = TIM_CKD_DIV1; TIM_1.TIM_CounterMode = TIM_CounterMode_Up; TIM_TimeBaseInit(TIM1,&TIM_1); TIM_ARRPreloadConfig(TIM1, ENABLE); /* Configures the TIM1 Channel1 */ OC_TIM_1.TIM_OCMode = TIM_OCMode_PWM1; OC_TIM_1.TIM_OutputState = TIM_OutputState_Enable; OC_TIM_1.TIM_OutputNState = TIM_OutputNState_Disable; OC_TIM_1.TIM_Pulse = 32768; OC_TIM_1.TIM_OCPolarity = TIM_OCPolarity_Low; OC_TIM_1.TIM_OCNPolarity = TIM_OCNPolarity_High; OC_TIM_1.TIM_OCIdleState = TIM_OCIdleState_Reset; OC_TIM_1.TIM_OCNIdleState = TIM_OCIdleState_Reset; TIM_OC1Init(TIM1, &OC_TIM_1); TIM_OC1PreloadConfig(TIM1, TIM_OCPreload_Enable); /* Enables the TIM counter */ TIM_CtrlPWMOutputs(TIM1, ENABLE); TIM_Cmd(TIM1, ENABLE); Thank you for your help.2013-04-24 04:39 AM
OC_TIM_1.TIM_Pulse = 0; // << Always OFF, pick something like 32768 for 50/50 duty
2013-04-24 04:44 AM
''OC_TIM_1.TIM_Pulse = 0;'' don't worry I'm not
thoughtless
, I modify after with TIM_SetCompare1.