Problem with internal flash EOP interrupt

justin239955_st · ‎2013-01-17

Posted on January 17, 2013 at 17:28

Hi,

I'm working on a project on the STM32F100 using the CodeSourcery GCC C compiler and linker in eclipse. I'm using some of the standard library from st. The project is almost done and using many timer, interrupts, dma but now i'm stuck on something.

I'm trying to add a module to save a big struct in flash page 127 using interrupt. I can erase the page and write to it, no problem. My problem is that I can't to get the interrupt on the internal flash EOP to trigger. Using the debugger i see that the EOPIE bit is set in FLASH->CR. Right after the erase command the EOP flag rises in the FLASH->SR register but no interrupt triggers. Anybody has an idea?

Here is the code:

void FlashInit(void) {

FLASH_Unlock();

FLASH_ClearFlag(FLASH_FLAG_EOP);

FLASH_ITConfig(FLASH_IT_EOP, ENABLE);

FLASH_ErasePage(0x0801FC00); // PAGE 127

FLASH_ProgramWord(0x0801FC00, 0x12345678);

FLASH_ProgramWord(0x0801FC02, 0xCAFEFADE);

}

void FLASH_IRQHandler(void) {

if(FLASH_GetFlagStatus(FLASH_FLAG_EOP) == SET) {

FLASH_ClearFlag(FLASH_FLAG_EOP);

}

Thanks for any help.

#stm32f100-interrupt-flash-eop

Tesla DeLorean · ‎2013-01-17

Posted on January 17, 2013 at 19:04

Enabled via NVIC?

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justin239955_st · ‎2013-01-17

Posted on January 17, 2013 at 19:57

Shoult it? I don't see any IRQ channel related to this interrupt... Should I map it through a EXTI IRQ?

Tesla DeLorean · ‎2013-01-17

Posted on January 17, 2013 at 20:55

NVIC_InitTypeDef NVIC_InitStructure;
NVIC_InitStructure.NVIC_IRQChannel = FLASH_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);

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justin239955_st · ‎2013-01-17

Posted on January 17, 2013 at 21:05

That's it. Thanks a lot.

It's my 1st project on ARM and I didnt realise that there are 3 kinds of IRQ:

Cortex-M3 specific

STM32 specific

and device specific

I was only looking at device specific in the include file.

Thanks again!

justin239955_st · ‎2013-01-17

Posted on January 17, 2013 at 21:49

If you still have 2 min I still have a question for my understanding.

1st I enable the interrupt with the flash module:

FLASH_ITConfig(FLASH_IT_EOP, ENABLE);

Then I need to configure the nvic to ''route'' the interrupt?

Without the configuration of the nvic, the interrupt gets to nvic but never calls the isr?

I've worked the past 6 years with the Motorola MC9S12 and the concept of nvic does not exists. You just flip a bit and the corresponding isr gets serviced.

Thanks for your time!

Tesla DeLorean · ‎2013-01-17

Posted on January 17, 2013 at 22:23

The FLASH_ITConfig(FLASH_IT_EOP, ENABLE); Is basically a peripheral level enablement, basically gating a status bit out as in interrupt source. At this level an AND gate, other sources within the peripheral are then OR'd together so the peripheral has ONE interrupt line.

The NVIC is a vectoring controller attached to the core, which can order and prioritize the interrupt sources. It is similar in some ways to the x86, and 68K auto vectoring.

With ARM you need to keep in mind that the peripherals are not part of the core, but vendor specific. Some peripherals, like the TIM units can use multiple interrupt vectors. The NVIC is an Cortex-Mx architected solution, and replaces some of the indirect vectoring schemes used in the ARM7 and 9, Atmel's AIC being a classic implementation of such.

Then there are of course core level ''exceptions'', like Abort, Hard Fault, and SysTick.

The NVIC configuration is more of a one time initialization, unless you want to play with priority levels. To change service routines you'd need to park the vector table in RAM.

The peripheral level is more one of appropriateness, with the USART you often want to disable the TXE interrupt if you don't have any data to satiate it. If you don't you can't clear the condition and it will keep re-entering the routine and preventing further foreground executions. This is often described as an interrupt storm. Watch for unserviced interrupts to dump you to the Hard Fault handler, or empty vectors to point to a while(1);

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justin239955_st · ‎2013-01-17

Posted on January 17, 2013 at 22:30

Ok thanks. See you around.