Problem in six-step PWM generatioin

[song]

Posted on August 23, 2016 at 04:36

I am using STM32F3 Discovery board to generate six-step PWM signals for BLDC motor drive. The switching was done in SysTick ISR by generating a SW COMG event. When I checked the PWM output on oscilloscope, however, I noticed that the very first PWM pulse generated was always much wider than the duty cycle I set, as shown in the picture attached.

I attached the code I used and would anyone please help to check why the wide first pulse could happen?

[waclawek.jan]

Posted on August 23, 2016 at 12:16

It's the combination of

TIM_SelectOCxM(TIM1, TIM_Channel_1, TIM_ForcedAction_Active);

andIn PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen� mode to “PWM� mode. JW

[Walid FTITI_O]

Posted on August 23, 2016 at 13:59

Hi David_Lin,

Try to set the UG bit of the TIMx_EGR register  before enabling the timer. This will force the Update event generation once the timer is enabled and preload the shadow register' values. -Hannibal-

[song]

Posted on August 25, 2016 at 02:49

Hi, Jan, thanks for the reply, and would you please suggest how I should change the code to avoid this problem?

[song]

Posted on August 25, 2016 at 03:27

Hi, Hannibal, do you mean adding TIM1 -> EGR |= 0x0001 to BLDCMotorPrepareCommutation() function? 

The logic of the switching is to prepare the TIM1 register values first and when the next SysTick ISR happens, the register values will be updated. If I were to add TIM1 -> EGR |= 0x0001, will it change the switching logic?