Priorities of Interruptions (Systick has the same priority as LTDC and other peripherals?)

[Ivan Ivan]

Posted on August 31, 2017 at 13:55

Hello. I'm using STM32F429I-DISC1 board and implementing a complex project with plenty of peripherals including a built-in screen using a provided HAL code.

I have stumbled upon some problem regarding the order of operations. While solving it I have wrote such experimental code:

uint32_t Systick_foundPriority = NVIC_GetPriority(SysTick_IRQn);
uint32_t SPI5_foundPriority = NVIC_GetPriority(SPI5_IRQn);
uint32_t LTDC_foundPriority = NVIC_GetPriority(LTDC_IRQn);
uint32_t LTDC_ER_foundPriority = NVIC_GetPriority(LTDC_ER_IRQn);
uint32_t DMA2D_foundPriority = NVIC_GetPriority(DMA2D_IRQn);�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?

I have expectedthese variables to have values defined in table 62 (Vector table for STM32F42xxx and STM32F43xxx), on p.376 of Reference Manual for

STM32F429 but they all appear to be equal to zero. NVIC_GetPriority refers to undocumented registers which look like NVIC->IPR (there are several of these).

I have checked out these registers in debugger, and only IPR14 had value of 0x000000F0 (IPR_N0), other were all zeros.

Is this a real place where IRQ priorities are stored?

Why the developers of screen-handling (BSP, HAL) code decided to put a maximal priority for screen-related activities?

Is it OK to change these priorities after screen has been initialized?

#nvic #stm32f429i-disc1

[Tesla DeLorean]

Posted on August 31, 2017 at 14:15

Don't think it's 'undocumented'

The function and structure are defined in here, it reads the values out of the NVIC IPR [+0x300, 0xE000E400]

Drivers\CMSIS\Include\core_cm4.h

System handlers are managed in the SCB

You'd always want the SysTick to preempt everything else given the criticality of the HAL_Tick, make sure the priority grouping is set up to enable that.

[waclawek.jan]

Posted on August 31, 2017 at 14:16

NVIC_GetPriority refers to undocumented registers which look like NVIC->IPR

They are documented in PM0214, 4.3  Nested vectored interrupt controller (NVIC) and the Cortex-M4 TRM

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0439b/Cihfihfe.html

and ARMv7M ARM

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0439b/Cihfihfe.html

 

The keyword you are looking for is priority grouping.

JW

[Ivan Ivan]

Posted on September 01, 2017 at 11:05

After reading article:

http://micromouseusa.com/?p=279

...and ARMv7 architecture manual (p B3-760) (mentioned in CortexM4 TRM),

I have constructed this code:

NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_2);
HAL_NVIC_SetPriority(SPI5_IRQn, 3, 1);
HAL_NVIC_SetPriority(DMA2D_IRQn, 3, 2);
HAL_NVIC_SetPriority(LTDC_IRQn, 3, 3);
HAL_NVIC_SetPriority(LTDC_ER_IRQn, 3, 4);�?�?�?�?�?�?�?�?�?�?

The priorities got changed as expected.

Thank you all.