Hello everyone,
I was reviewing the AN4899 Application Note and noticed a potential logic inconsistency that might lead to misunderstanding the GPIO output stage. I have prepared a short analysis and a proposed correction below. I would appreciate it if the technical team could take a look.
Introduction
This report investigates a potential logic inconsistency identified in the STMicroelectronics
AN4899 Application Note. The analysis suggests that the logic gates in Figures 15, 16
and 17 might be drawn incorrectly, specifically the part controlling the P-MOS transistor. Due
to the structural similarities between these figures, the analysis is explained based on Figure
17.
Signal Mapping and Logic Analysis
The following diagram (Figure 1) has been labeled with signal names to track the logic flow
from the digital output to the transistor gates:
Figure 1: Labeled Figure 17 from STMicroelectronics AN4899 Application Note. Red arrows and signal labels
(SIGN1-SIGN6) have been added for logic analysis.
Upon reviewing the signal flow in Figure 1, several unexpected behaviors are observed
when the documented AND gates are used. These inconsistencies include potential
shoot-through currents in Push-pull mode and operational failures in Open-drain mode.
The truth table (Figure 2) below illustrates the unexpected transistor states resulting from the
two-AND-gate configuration:
Figure 2
Figure 2: Truth table illustrating the logical consequences of the original AND gate configuration in
Figure 17. > Analysis shows that using the documented AND gates results in unintended "Short Circuit" states
where both P-MOS and N-MOS transistors conduct simultaneously.
Proposed Solution
Figure 3
Figure 3: Original Logic Diagram from AN4899 with Proposed Correction The red arrow
indicates the upper AND gate that should be implemented as a NAND gate.
To solve these problems, the upper control gate should be a NAND gate instead
of an AND gate. This change ensures the transistors work correctly according to
STM32 standards. Although not explicitly shown in Figure 17, this analysis
assumes that the Digital Output signal is the inverted (opposite) value of the
Output Data Register (ODR). This assumption is necessary to align the
software-side register values with the hardware-side transistor logic.
As shown in the corrected truth table below, using a NAND gate with this logic
works for all GPIO modes:
Figure 4
Figure 4: Corrected Truth Table using a NAND Gate for P-MOS Control. This table demonstrates the logical
results of replacing the upper AND gate with a NAND gate.
1 ACCEPTED SOLUTION
Accepted Solutions
