Possible to continuously ADC sample only during active phase of PWM? (STM32F466RE)

[norlesh]

I'm using an STM32F466RE to drive a motor via PWM and want to sample a current monitor via ADC during the active part of the pulse so that I can integrate the amount of power delivered to the motor. This will require the sample rate to be high enough to obtain samples during the minimum pulse witdth (1/100 of PWM period) and what I'd like is to prevent the ADC from capturing wasted samples during the off part of the pulse since that would just be a heap of zeroes that need to be integrated.

Is there any way to configure the device so that continuous ADC sampling is gated by the state of the PWM output? Or will I have to sample continuously and figure out what to ignore?

At the moment I'm planning on driving the PWM at ~500Hz, sampling at ~50kHz, and using the calculated power in a control loop updated at maybe ~50Hz.

[waclawek.jan · Accepted solution]

Output the PWM channel as TRGO from this timer. Use another suitable timer as a slave, set its TRGI to the PWM timer, set its slave-controller mode to gated, set it up to the have a period as required for the ADC sampling rate and use it to trigger ADC.

JW

[norlesh]

Thanks, I think that makes sense - am now going over the Timer Cookbook (AN4776) to figure out how to implement your suggestion, this has given me a new appreciation for the generality of the timer blocks.

[norlesh]

Figured I would report back on the configuration for the benefit of anyone facing a similar challenge now I know that it works.

Using the NUCLEO-F446RE I have set TIM2 as master to generate a 500Hz PWM signal (output on PA5 which corresponds to the on board user LED) and Trigger Output (TRO) is using OC1REF to express the active phase of the pulse.

TIM3 is set in gated slave mode using ITR1 as the trigger source connected from TIM2, Channel1 is set to Output Compare (with the output driving PA6 so I could check it on an oscilloscope) Output Compare of CH1 is set to Toggle on match producing a square wave that triggers the ADC on both edges. The timing is setup so I have 100kHz (this gives me two samples for every 1% of PWM value).

ADC1 is configured with "Timer 3 Trigger Out event" and "Trigger detection on both the rising and falling edges", DMA continuous requests are enabled and a DMA transfer configured.

Well, good luck to anyone else attempting to gate there ADC sampling - hope these notes give some clues. [and thanks again to JW for pointing out the strategy]