2019-02-06 06:50 AM
2019-02-06 08:23 AM
All the STM32 have an SPI controller capable of interfacing SPI FLASH devices.
L4, F7 and H7 have QuadSPI (QSPI) controllers to map the external memory in a usable fashion. Check out a couple of the DISCO and EVAL boards for working examples. The L4+, and perhaps others, support OctoSPI (OSPI) for improved bandwidth.
2019-02-06 07:24 PM
The QSPI interface offers some nice features over regular SPI, especially if it's a read mostly application. QSPI can map the entire NOR into the STM32 memory space. Once configured reads to a memory address automatically fetch the data from flash with look-ahead.
QSPI also has automated polling for erase/write completion, saves a lot of CPU polling time. QSPI also supports DDR mode on some ICs along with 4-bit mode, up to 8x transfer rates compared to SPI.
OctoSPI interleaves two NOR flash ICs so you can transfer 2x4-bit data on every clock edge, 16x over an SPI bus.
Jack Peacock