With the following code to handshake an EEPROM
STM_enableRCCAPB1PeriphClock( RCC_APB1Periph_I2C1, ENABLE );
STM_resetRCCAPB1PeriphCmd( RCC_APB1Periph_I2C1, DISABLE );
I2C_Cmd( m_pEE_I2C_TYPE, ENABLE );
I2C_ITConfig( m_pEE_I2C_TYPE, I2C_IT_ERR, ENABLE );
I2C_InitStructure.I2C_Mode = EE_I2C_MODE;
I2C_InitStructure.I2C_DutyCycle = EE_I2C_DUTY_CYCLE;
I2C_InitStructure.I2C_OwnAddress1 = EE_I2C_OWN_ADDRESS;
I2C_InitStructure.I2C_Ack = EE_I2C_ACK;
I2C_InitStructure.I2C_AcknowledgedAddress = EE_I2C_ACK_ADDR;
I2C_InitStructure.I2C_ClockSpeed = EE_I2C_CLOCK_SPEED;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 BITOR GPIO_Pin_7;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
/* Generate the START condition */
I2C1->CR1 |= I2C_CR1_START;
/* wait until START condition is set */
while ( NOT ( I2C1->SR1 BITAND I2C_SR1_SB ) )
{
}
/* send the address of the EEPROM with r/w-bit reset */
address = EE_EXT_ADDRESS;
address |= 1u; // read / receiver
I2C1->DR = address;
/* wait for either ADDR (ACK) oder AF (NACK) to be set */
u16StatusRegister = 0x00u;
while ( NOT ( ( u16StatusRegister BITAND I2C_SR1_ADDR ) BITOR (
u16StatusRegister BITAND I2C_SR1_AF ) ) )
{
u16StatusRegister = I2C1->SR1;
}
I see the rising of either AF or ADDR in the debugger's register view after executing
I2C1->DR = address, but as soon as I execute u16StatusRegister = 0x00u, all bits in SR1 are reset.
Could anybody guess why that's happening?
I'm using IAR workbench 7.50 and IAR I-jets debugger on a STM32f103, and there are no interrupt routines coded.
