Posted on December 21, 2016 at 20:00I spent some time working with Philips IC Test and QA groups
I don't know the methodologies at ST, but suspect there will be some die level testing, and packaged testing. The wafer is also likely to have some parametric cells or test sites, and a singular device or sample might be more intensively tested than others.
I think the factors impacting flash test time will be the time to perform a parallel erase (mass erase), and then how many of the sectors are subsequently tested in some kind of high/low write patterns. The F4 1MB and 2MB die being quite expensive in seconds on the test machine. The choice to make 256KB parts resulting from a choice not to spend time testing beyond that, rather than binning devices failing at some point below the full capacity.
I'm leaning toward the cost driver for the F0 playing a role in the design choices and less redundancy in the flash array, which shrinks the die size, and increases the die per wafer.
The FLASH+RAM using a significant area of the die, the peripheral logic also being quite large with respect to the Cortex-M0 core itself.
