2022-12-20 11:50 AM
Hello guys, I have a problem with my project. I'm development the PS/2 (device, keyboard-like) protocol with my STM32F103C8T6 (Bluepill). When i convert my port to the open collector output, the noise appear in the PS/2 bus. In this moment, the STM32 controll de clock/data bus. I used open-collector to control de bus. I have a 10K resistor to pull-up the bus.
For exemple: (0x1A data every second)
Basically, this is my routine to generate the clock and data:
clk_out; //PB10 -> Clock (Vai pra 1 no bit 10 e pra 0 no 26)
dt_out; //PB11 -> Data (Vai pra 1 no bit 11 e pra 0 no 27)
bit0_dt;
btempo40us;
bit0_clk;
btempo20us;
for(unsigned char x = 0; x < 8; x++){
btempo20us;
bit1_clk;
btempo20u
if( dado & (1 << x) ){
bit1_dt;
paridade++;
}else{
bit0_dt;
}
btempo20us;
bit0_clk;
btempo20us;
}
btempo20us;
bit1_clk;
if(paridade % 2 == 0){
bit1_dt;
}else{
bit0_dt;
}
btempo40us;
bit0_clk;
btempo40us;
bit1_clk;
bit1_dt;
btempo40us;
bit0_clk;
btempo500us;
bit1_clk;
bit1_dt;
dt_in;
clk_in;
Below, this is my macro used in this code above:
#define btempo40us TIM3->ARR = 39;\
TIM3->CR1 |= (1 << 0);\
while( TIM3->CR1 &(1 << 0) ){}
#define btempo100us TIM3->ARR = 99;\
TIM3->CR1 |= (1 << 0);\
while( TIM3->CR1 &(1 << 0) ){}
#define btempo20us TIM3->ARR = 18;\
TIM3->CR1 |= (1 << 0);\
while( TIM3->CR1 &(1 << 0) ){}
#define btempo50us TIM3->ARR = 49;\
TIM3->CR1 |= (1 << 0);\
while( TIM3->CR1 &(1 << 0) ){}
#define btempo500us TIM3->ARR = 499;\
TIM3->CR1 |= (1 << 0);\
while( TIM3->CR1 &(1 << 0) ){}
#define read_clk (GPIOB->IDR &(1 << 10)) // Macro pra ler o pino de clock
#define read_dt (GPIOB->IDR &(1 << 11)) // Macro pra ler o pino de data
#define clk_in GPIOB->CRH &= ~( (1 << 9) | (1 << 8) );\
GPIOB->CRH &= ~(1 << 10);\
GPIOB->CRH |= (1 << 11);\
GPIOB->ODR |= (1 << 10);
#define clk_out GPIOB->CRH &= ~( (1 << 11) | (1 << 10) );\
GPIOB->CRH |= (1 << 10);\
GPIOB->CRH |= (1 << 8) | (1 << 9);\
GPIOB->ODR |= (1 << 10);
#define dt_in GPIOB->CRH &= ~( (1 << 13) | (1 << 12));\
GPIOB->CRH &= ~(1 << 14);\
GPIOB->CRH |= (1 << 15);\
GPIOB->ODR |= (1 << 15);
#define dt_out GPIOB->CRH &= ~( (1 << 15) | (1 << 14) );\
GPIOB->CRH |= (1 << 14);\
GPIOB->CRH |= (1 << 13) | (1 << 12);\
GPIOB->ODR |= (1 << 15);
#define bit1_clk GPIOB->ODR |= (1 << 10);
#define bit0_clk GPIOB->ODR &= ~(1 << 10);
#define bit1_dt GPIOB->ODR |= (1 << 11);
#define bit0_dt GPIOB->ODR &= ~(1 << 11);
I don't know what is causing these noises. :worried_face::worried_face:
When I use the push-pull output the noise disappears... But, this is not recommended.
Thank you!
Solved! Go to Solution.
2022-12-20 01:02 PM
you pics show a strong capacitive coupling between clk and data ( y + cyan) , so separate the lines or screen them separately;
if using a flat cable , try : gnd/clk/gnd/data/gnd . so get some "screen" by the gnd lines.
2022-12-20 01:02 PM
you pics show a strong capacitive coupling between clk and data ( y + cyan) , so separate the lines or screen them separately;
if using a flat cable , try : gnd/clk/gnd/data/gnd . so get some "screen" by the gnd lines.
2022-12-20 03:51 PM
I'm using the protoboard, maybe it's the low quality of it. I will check this and I return with news! 👍
2022-12-20 04:12 PM
The problem is the protoboard! Thank you very much for help! :(
2022-12-20 05:09 PM
Maybe you created some ground loop, which can be a problem.