new STM32H7B3 and SRAM quantities

[PCu1]

Hello,

I have a doubt about the amount of SRAM available on the STM32H7B3.

In the datasheet it is indicated 1184kB (setion embedded SRAM), but the linker script indicates 1024kB.

In the datasheet, there is not much detail on this.

My goal is to use for a frame buffer for 480 x 800 x 3(24-bit) = 1152kB

So I avoid an external RAM...

Kind regards,

Pierre

[Ozone]

> My goal is to use for a frame buffer for 480 x 800 x 3(24-bit) = 1152kB

> So I avoid an external RAM...

I don't think so.

Take a closer look at the datasheet, sect. 3.3.3. Embedded SRAM.

It says:

• 1 Mbyte of AXI-SRAM mapped onto AXI bus matrix in CPU domain (CD) split into:

– AXI-SRAM1: 256 Kbytes

– AXI-SRAM2: 384 Kbytes

– AXI-SRAM3: 384 Kbytes

• 128 Kbytes of AHB-RAM mapped onto AHB bus matrix in CPU domain (CD) split into:

– AHB-SRAM1: 64 Kbytes

– AHB-SRAM2: 64 Kbytes

• 32 Kbytes of SRD-SRAM mapped in Smart Run Domain (SRD)

• 4 Kbytes of backup SRAM

The reference manual, sect. 2.4 Embedded SRAM, page 134, lists the addresses of each block:

The embedded system SRAM is divided into up to six blocks:

• CD domain, AXI SRAM:

– AXI SRAM1 mapped at address 0x2400 0000

– AXI SRAM2 mapped at address 0x2404 0000

– AXI SRAM3 mapped at address 0x240A 0000

All AXI SRAMs can be accessed by all system masters through the AXI bus matrix

except BDMA1 and BDMA2.

• CD domain, AHB SRAM:

– AHB SRAM1 mapped at address 0x3000 0000

– AHB SRAM2 mapped at address 0x3001 0000

All the AHB SRAMs can be accessed by all system masters through the CD AHB

matrix except for BDMA2.

• SRD domain, SRD SRAM:

– SRD SRAM is mapped at address 0x3800 000

[PCu1]

Thank you Ozone.

I missed section 3 because I was on section 4 where it is indicated to consult RM0455.

Memory are not contiguous.

1024K is too low to use my screen in 24-bit...

[Ozone]

Such a fragmented memory layout is quite normal for a MCU.

If your application is mainly display/graphics, I would consider a Cortex A or similar.

Cortex A5 are similar in price, but come with MMU and thus a "proper" OS, and (more or less) unlimited RAM sizes.

[berendi]

AXI SRAM1/2/3 present a contiguous 1024k memory area, AHB SRAM1/2 present a contiguous 128k memory area. It is possible to split the framebuffer between them.

• Using the two layers of the LTDC controller, split the framebuffer at a line boundary, so one layer gets its pixel data from AXI SRAM, the other from AHB SRAM. Just position one layer directly below the other to cover the whole screen. It makes drawing to the framebuffers a bit awkward, but definitely works.
• The GFXMMU unit is apparently designed for just this purpose, but I don't have any experience using it.

> 480 x 800 x 3(24-bit) = 1152kB

480 x 800 x 3(24-bit) = 1152000 bytes = 1125 kB.

Adjust the linker script to place program variables into DTCM RAM (128k), and use the remaining 27 kbytes of AXI/AHB SRAM for DMA buffers if there would be any.