Need to use SDRAM for heap and stack and for that it needs to be up before main function

shashank78Khandve · ‎2026-05-10

I am working on SDRAM execution using FMC on STM32H563ZI (NUCLEO-H563ZI board) with external SDRAM connected through FMC interface.

Our target is:

Execute application sections from SDRAM
Place heap and stack in SDRAM
Enable automatic scatter-loading/copy from internal flash to SDRAM during startup

We are facing an issue where:

SDRAM initialization appears successful
Manual SDRAM read/write access works in application runtime
But automatic copy/scatter-loading from Flash to SDRAM during startup is failing
Application execution from SDRAM is unstable and leads to HardFault/reset handler

Below are the detailed steps and observations.

CURRENT STARTUP FLOW

Reset_Handler
→ SystemInit()
→ PLL/System clock configuration
→ FMC GPIO configuration
→ FMC SDRAM initialization
→ SDRAM command sequence
→ __main()
→ scatter loading
→ main()

We intentionally moved FMC/SDRAM initialization into SystemInit() so that SDRAM becomes available before scatter loading.

CLOCK CONFIGURATION

We configured PLL through direct register-level programming.

Configuration:

HSE used as PLL source
HSE = 25 MHz
PLLM = 5
PLLN = 36
PLLR = 2
SYSCLK = 90 MHz

PLL configuration registers used:

RCC->PLL1CFGR
RCC->PLL1DIVR
RCC->CFGR1

We observed:

System boots successfully
main() is reached correctly
FMC clock is enabled
SDRAM initialization sequence executes

However, execution from SDRAM still fails.

We suspect there may be an FMC kernel clock stabilization issue immediately after SYSCLK switching from HSE/HSI to PLL.

FMC GPIO CONFIGURATION

All FMC pins are configured through direct register-level configuration (without HAL).

Configured pins include:

Address lines A0-A11
Data lines D0-D15
BA0/BA1
SDCLK
SDCKE0
SDNE0
SDNRAS
SDNCAS
SDNWE
NBL0/NBL1

GPIO configuration:

Alternate Function AF12
Push-pull
Very high speed
No pull-up/pull-down

GPIO clocks enabled:

GPIOA
GPIOC
GPIOD
GPIOE
GPIOF
GPIOG

FMC clock enabled through RCC->AHB4ENR.

SDRAM CONFIGURATION

SDRAM configuration:

SDRAM Bank 1
16-bit data width
4 internal banks
8-bit column address
12-bit row address
CAS latency = 3
SDRAM clock period = 2 HCLK cycles
Read pipe delay = 1

Timing configuration used:

TMRD = 2
TXSR = 3
TRAS = 2
TRC = 3
TWR = 2
TRP = 1
TRCD = 3

These values are based on CubeMX-generated settings.

SDRAM COMMAND SEQUENCE

The following sequence is executed:

Clock enable command
Delay
Precharge all command
Auto-refresh command
Load mode register command
Refresh rate programming

Refresh rate currently configured approximately around:
683 (based on 90 MHz FMC clock)

MPU CONFIGURATION

MPU region configured for SDRAM:

Base address = 0xC0000000
Size = 8MB
Full access
Non-cacheable configuration currently used for initial bring-up

OBSERVED BEHAVIOR

Observed results:

SDRAM initialization completes
Manual SDRAM write/read test works after main()
Direct pointer-based SDRAM access also works
FMC registers appear correctly configured

However:

Scatter loading to SDRAM during startup fails
Application execution from SDRAM fails
Heap/stack placement in SDRAM causes instability
LED task execution eventually enters HardFault/reset handler

This suggests SDRAM works during later runtime but may not be stable during early startup/scatter loading.

CURRENT SUSPICIONS

We suspect one or more of the following:

FMC kernel clock stabilization issue after SYSCLK switch
SDRAM clock enable timing requirement not met during early startup
SDRAM stabilization delay insufficient before scatter loading
Additional startup sequencing requirement on STM32H563 FMC/SDRAM
Scatter-loading/runtime startup dependency before SDRAM becomes fully stable
Missing FMC/AXI/cache synchronization requirement
Requirement to keep stack/heap internal during scatter loading stage

REQUEST FOR GUIDANCE

We request support regarding:

Correct recommended startup sequence for SDRAM execution on STM32H563
Whether SDRAM initialization inside SystemInit() is officially supported
Any required stabilization delays before __main()/scatter loading
Any FMC clock synchronization requirements after PLL switch
Recommended MPU/cache settings for SDRAM execution
Recommended scatter file configuration for SDRAM execution
Whether any additional FMC initialization steps are required on STM32H5 series

Please let us know if you need:

Full source code
Scatter file
SDRAM datasheet
FMC register dump
CubeMX project
Debug screenshots

Thanks & Regards,

Shashank Khandve

mƎALLEm · ‎2026-05-11

Hello @shashank78Khandve and welcome to the ST community,

I cannot help you in the SDRAM calculation timings and parameter, meanwhile you can refer to this article / example: How to set up the FMC peripheral to interface with the SDRAM IS42S16800F-6BLI from ISSI

Also, I'm wondering how are you connecting an SDRAM to the NUCLEO. You need to take care about the signal integrity aspects as high frequencies are involved. Refer to this article: How to avoid signal integrity issues on the STM32H7R7/S7 and AN4803 "High-speed SI simulations using IBIS and board-level simulations using HyperLynx® SI on STM32 MCUs and MPUs".

For scatter loading, your process seems to be correct. SDRAM and its respective GPIOs need to be initialized before main(), i.e. in SystemInit(). Unfortunately there is no example available on STM32H5 for this scenario but STM32H743, has such implementation in the HAL, especially in system_stm32h7xx.c

You need to look at blocks where DATA_IN_ExtSDRAM is defined.

Meanwhile, the SDRAM region in STM32H5 is in the range of 0xC000 0000 to 0xDFFF FFFF, according the reference manual RM0481:

While, by default, the region is in execute never configuration (XN), according to the programming manual PM0264:

So most probably that's why you are facing a hard fault while executing from SDRAM. You should configure that region to make it executable using the MPU before jumping to the main.

Hope that helps.

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