Introduction
While designing high-speed embedded systems with the STM32H7R7/S7 series, signal integrity is a critical factor to ensure reliable operation and optimal performance. Signal integrity refers to the quality and fidelity of electrical signals as they travel through the PCB traces, connectors, and interfaces. Poor signal integrity can lead to data corruption, increased error rates, and system instability.
- Introduction
- 1. Signal Integrity (SI)
- 1.1 Impedance mismatches
- 1.2 Crosstalk
- 1.3 Noise
- 1.4 Jitter
- 2. Why signal integrity matters
- 3. Best practice for maintaining signal integrity
- 4. Recommended PCB routing/hardware guidelines for STM32H7Rx/7Sx microcontrollers
- 4.1 Printed circuit board
- 4.2 Component position
- 4.3 Ground and power supply (Vss, VDD)
- 4.4 PCB stack-up
- 4.5 Power supply decoupling
- Conclusion
- Related links
1. Signal Integrity (SI)
Signal integrity (SI) refers to the ability of a system to transfer data signals without excessive distortion. Signal degradation occurs in all systems, but maintaining signal integrity becomes increasingly important at higher speeds, which correspond to shorter rise times.
These shorter rise times result in higher frequency components within the signals. Although the term "high speed" is not strictly defined, it generally refers to rise times on the order of approximately 1 nanosecond (ns). Consequently, signal integrity is a critical consideration in high-speed digital design to ensure reliable and accurate data transmission.
The sources of transmission line degradations include several key factors.
1.1 Impedance mismatches
These occur when the impedance between different parts of the transmission channel is not properly matched, causing signal reflections that degrade the signal quality:
- Changes in trace dimensions/geometry
- Improper terminations/unterminated stubs
- Via characteristics (hole size, pad sizes, etc.)
- Discontinuities/return path
- Variations in board materials
Figure 1. PCB traces
1.2 Crosstalk
This is the unwanted coupling of signals between adjacent conductors or traces in a circuit, where the signal transmitted on one channel (known as the aggressor) induces an undesired signal in a neighboring channel (known as the victim). This phenomenon occurs primarily due to the electromagnetic interactions between the conductors, specifically through mutual inductance and mutual capacitance.
Mutual inductance causes crosstalk when a changing current in the aggressor trace generates a magnetic field that induces a voltage in the victim trace.
Mutual capacitance leads to crosstalk when the electric field between adjacent conductors allows a portion of the signal’s voltage to couple across, transferring energy from the aggressor to the victim.
Crosstalk is categorized into two types based on where the interference is observed relative to the aggressor signal.
Near-end crosstalk (NEXT): The interference appears at the receiving end of the victim trace closest to the aggressor’s transmitter.
Far-end crosstalk (FEXT): The interference appears at the far end of the victim trace, away from the aggressor’s transmitter.
The severity of crosstalk increases with faster signal rise times because rapid voltage changes generate stronger electromagnetic fields, which more readily couple into adjacent traces.
1.3 Noise
External or internal noise sources introduce unwanted variations in the signal, which can distort the data and reduce the overall signal integrity.
1.4 Jitter
A jitter is the variation or deviation in the timing of a digital signal’s transitions relative to their ideal positions. In digital communication systems, signals are sampled at precise, predefined bit times to interpret the transmitted data correctly. For accurate data recovery, signal transitions (the changes from logical 0 to 1 or vice versa) must occur within specific timing windows between these sample points.
When jitter is present, these transitions shift in time, causing the signal to arrive either earlier or later than expected. This timing variation can lead to several issues:
Incorrect sampling: If a signal transition occurs too close to or during the sampling instant, the receiver may sample an undefined or intermediate voltage level rather than a clear logical ‘0’ or ‘1’.
Bit errors: Such incorrect sampling results in bit errors, where the received data differs from the transmitted data, degrading communication reliability.
Timing uncertainty: Jitter introduces uncertainty in the timing margin, reducing the tolerance for noise and other impairments.
There are several types of jitters, each with distinct characteristics:
Data-dependent jitter (DDJ): This jitter depends on the data pattern being transmitted. Certain bit sequences cause more timing variation due to phenomena like intersymbol interference (ISI), where previous bits affect the current bit’s timing.
Periodic jitter (PJ): This jitter occurs in a repetitive, predictable pattern, often caused by periodic interference sources such as power supply noise or crosstalk from nearby signals.
Random jitter (RJ): This jitter is caused by random noise sources and is statistically unpredictable. It typically follows a gaussian distribution and can accumulate over time.
2. Why signal integrity matters
The STM32H7R7/S7’s fast external memory interfaces increase susceptibility to signal degradation issues such as:
- Reflections: Caused by impedance mismatches on high-speed lines, resulting in signal echoes that distort the original waveform.
- Crosstalk: Electromagnetic interference between adjacent signal traces can cause unwanted noise and data errors.
- Ground bounce and power noise: Fluctuations in ground and power lines can affect signal thresholds and timing.
- Electromagnetic interference (EMI): High-speed signals can radiate noise that interferes with other system components or violates regulatory limits.
3. Best practice for maintaining signal integrity
To mitigate signal integrity challenges in STM32H7R7/S7-based designs, consider the following guidelines:
- Controlled impedance PCB design: Use impedance-controlled traces for high-speed signals, matching the characteristic impedance of transmission lines to minimize reflections.
- Proper termination: Implement series or parallel termination resistors close to the source or load to dampen signal reflections.
- Trace routing: Keep high-speed signal traces short and avoid sharp bends; maintain adequate spacing between traces to reduce crosstalk.
- Ground and power planes: Use continuous ground and power planes to provide low inductance return paths and reduce noise coupling.
- Decoupling capacitors: Place capacitors close to power pins to stabilize voltage levels and filter out noise.
- Differential signaling: Where applicable, use differential pairs for critical signals to improve noise immunity.
- Signal integrity simulation: Utilize simulation tools during PCB design to predict and correct potential signal integrity issues before fabrication. [It is recommended using the IBIS model for simulation]
4. Recommended PCB routing/hardware guidelines for STM32H7Rx/7Sx microcontrollers
4.1 Printed circuit board
For technical reasons, it is best to use a multilayer printed circuit board (PCB) with a separate layer dedicated to the ground (VSS), and another dedicated to the VDD supply.
This provides both good decoupling and good shielding effect. For many applications, cost reasons prohibit the use of this type of board. In this case, the major requirement is to ensure a good structure for the ground and the power supply.
4.2 Component position
A preliminary layout of the PCB must separate the different circuits according to their EMI contribution to reduce the cross-coupling on the PCB (noisy, high-current circuits, low-voltage circuits, and digital components).
4.3 Ground and power supply (Vss, VDD)
Every block (such as noisy, low-level sensitive, and digital) must be grounded individually. All ground must return to a single point. Loops must be avoided or have a minimum area. The power supply must be implemented close to the ground line to minimize the supply loop area. This is because the supply loop acts as an antenna, and therefore becomes the EMI main transmitter and receiver. All component-free PCB areas must be filled with additional grounding to create adequate shielding (especially when using single-layer PCBs).
4.4 PCB stack-up
To reduce the reflections on high-speed signals, the impedance between the source, sink, and transmission lines must be matched. The impedance of a signal trace depends on its geometry and its position with respect to any reference plane.
The trace width and spacing between differential pairs for a specific impedance requirement is dependent on the chosen PCB stack-up. As there are limitations in the minimum trace width and spacing, which depend on the type of PCB technology and cost requirements, a PCB stack-up needs to be chosen which addresses all the impedance requirements.
The minimum configuration that can be used is four- or six-layers stack-up. An eight-layer board may be required for very dense PCBs that have multiple SDRAM/SRAM/NOR/LCD components. The following stack-ups (See the two figures below) are intended as examples, which can be used as guidelines for a stack-up evaluation and selection.
These stack-up configurations place the GND plane next to the power plane to increase the capacitance and reduce the physical gap between GND and the power plane. So, high-speed signals on the top layer have a solid GND reference plane, which helps reduce the EMC emissions. Therefore, moving up in the layers and having a GND reference for each PCB signal layer improves the radiated EMC performance.
4.5 Power supply decoupling
An adequate power decoupling for STM32H7Rx/7Sx MCUs is necessary to prevent excessive power and ground bounce noise. The following recommendations must be followed:
• Place the decoupling capacitors as close as possible to the power and ground pins of the MCU. For BGA packages, it is recommended to place the decoupling capacitors on the opposing side of the PCB.
• Add the recommended decoupling capacitors to as many VDD/VSS pairs as possible.
• Connect the decoupling capacitor pad to the power and ground plane with a wide and short trace/via. This reduces the series inductance, maximizes the current flow, and minimizes the transient voltage drops from the power plane and in turn reduces the ground bounce occurrence.
All the power supplies and ground pins must be properly connected to the power supplies. These connections, including pads, tracks, and vias must have the lowest possible impedance. This is typically achieved with thick track widths and, preferably, the use of dedicated power supply planes in multilayer PCBs. In addition, each power supply pair must be decoupled with filtering ceramic capacitors (100 nF) and one single ceramic capacitor (min. 4.7 μF) connected in parallel. These capacitors need to be placed as close as possible to, or below, the appropriate pins on the underside of the PCB. Typical values are 10 nF to 100 nF, but the exact values depend on the application needs.
Conclusion
The STM32H7R7/S7 microcontroller series offers a powerful platform for developing high-performance embedded applications with advanced graphical capabilities and robust memory architecture. However, to fully harness its potential, careful attention to signal integrity is essential, especially when working with high-speed external memory interfaces. By applying sound PCB design principles and leveraging the MCU’s built-in features, engineers can ensure reliable, high-speed operation and create innovative products that meet the demands of modern embedded systems.
