Modifying Open drain and push pull frequency of I3C messages with appropriate duty cycle

[Asfand]

Hi
How can we define separate frequency for open drain and push pull modes for I3C communication ?

In the documentation only the low phase is mentioned but for high phase there's no separate option for OD & PP modes.

Ideally I would like to do something like this 

<Context> I am working with  STM32H5RB03 as the controller and a MEMS sensor as the target. I want to do I3C communication at 12.5Mhz but the initial OD phase should have much lower frequency(<2Mhz) in order for the sensor to ACK(respond). I'm a newbie so might make basic mistakes while formulating my question, please ask if you need more clarity.

[Foued_KH]

Hello @Asfand , 

You can't define separate frequency for open drain and push pull modes for I3C communication in STM32CubeMx.
So after generate code, you should set the desired frequency 

/* Set bus speed to 1MHz for example*/
LL_I3C_CtrlBusConfTypeDef CtrlBusConf;
/* Calculate the new timing for Controller */
I3C_CtrlTimingComputation(&CtrlBusConf,
                           HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I3C1),
                           1000000,
                           0,
                           50,
                           I3C_PURE_I3C_BUS);
/* Update Controller Bus characteristic */
HAL_I3C_Ctrl_BusCharacteristicConfig(&hi3c1, &CtrlBusConf);

after you can change it, before the transfer : 

/* Set bus speed to 5MHz for example*/
/* Calculate the new timing for Controller */
I3C_CtrlTimingComputation(&CtrlBusConf,
                           HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I3C1),
                           5000000,
                           0,
                           50,
                           I3C_PURE_I3C_BUS);
/* Update Controller Bus characteristic */
HAL_I3C_Ctrl_BusCharacteristicConfig(&hi3c1, &CtrlBusConf);

Hope it helps!
Foued

[Asfand]

Hi @Foued_KH 
Thanks for the prompt reply.
I am using STM32CUBEIDE and it can not recognize the function 'I3C_CtrlTimingComputation' & definition 'I3C_PURE_I3C_Bus'. I have generated the example 'I3C Controller Inband interrupt' from STM32CubeMx by selecting appropriate board(not using example from Git repo).
Are these functions/definitions not included when we generate code from STM32CubeMx? If yes, can you point to the specific files I should look for ?
For ref:

Let me know If I'm missing something.

Regards,

Asfand

[Foued_KH · Accepted solution]

Hello @Asfand , 

Sorry ! The I3C_CtrlTimingComputation function is not available in the I3C files .

But you can just define LL_I3C_CtrlBusConfTypeDef and add the parameters for the new timing : 

This mean, configure the parameters SDAHoldTime, WaitTime, SCLPPLowDuration, SCLI3CHighDuration, SCLODLowDuration, SCLI2CHighDuration, BusFreeDuration, BusIdleDuration in the LL_I3C_CtrlBusConfTypeDef structure through i3c Init structure.
Then call : 
HAL_I3C_Ctrl_BusCharacteristicConfig(I3C_HandleTypeDef *hi3c,const LL_I3C_CtrlBusConfTypeDef *pConfig); 

Foued

[Asfand]

Hi @Foued_KH 
I'm able to change the frequency in between the code which is very useful. Thanks!
But the initial question the remains i.e. In one I3C message how can the frequency be varied by the controller in OD and PP phase. Usually the other controllers do this by themselves(not sure how, might be some sort of config).

The LL_I3C_CtrlBusConfTypeDef type has the same parameters as mentioned in the first post and lack the separate High Duration parameter for OD & PP.

Maybe following snap will help in clarification of what I'm trying to say.

Thank you for the support.

Regards,

Asfand

[Foued_KH]

Hello @Asfand 
I will share with you an example and let me know if this is helpful or not : 

Best Regards,
Foued

[Asfand]

EDIT: With uneven duty cycle, i am able to achieve the desired functionality. So turns out these parameters are good enough. 

Also the according to info on wikipedia this change in duty cycle is normal/must.
"

SCL is a conventional digital clock signal, driven with a push-pull output by the current bus controller during data transfers. (Clock stretching, a frequently used I²C feature, is not supported.) In transactions involving I²C target devices, this clock signal generally has a duty cycle, of approximately 50%, but when communicating with known I3C targets, the bus controller may switch to a higher frequency and/or alter the duty cycle so the SCL high period is limited to at most 40 ns.

"

Hi @Foued_KH 
Thank you for the reply.

After reading the definitions. I do not see a way of producing the desired waveform using these parameters. As the frequency difference(for ex:12Mhz-500khz) would result in a stretched duty cycle.

Regards,
Asfand