Posted on May 17, 2011 at 14:00First of all thanks for the quick response.
/* ============================================================ */
/* ============================================================ */void CLK_configuration (void) {
/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
/* ~~~~~~~~~~~~~~~~~~~~~~~~~~ HSI RC (8 MHz) ~~~~ */
RCC_HSICmd(ENABLE); /* ENABLE/DISABLE RCC_CR.HSION - INTERNAL 8MHz OSCILLATOR ON */
while(RCC_GetFlagStatus(RCC_FLAG_HSIRDY) == RESET); /* WAIT TO HARDWARE OFF */
RCC_SYSCLKConfig(RCC_SYSCLKSource_HSI); /* MODIFICA RCC_CFGR.SW - ELIGE EL HSI COMO SYSCLK SOURCE */
/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
/* ~~~~~~~~~~ HSE_Value (8 MHz) stm32f10x_conf.h ~~~~ */
RCC_HSEConfig(RCC_HSE_ON); /* ON/OFF RCC_CR.HSEON - EXTERNAL 8MHz OSCILLATOR ON */
while(RCC_GetFlagStatus(RCC_FLAG_HSERDY) == RESET); /* WAIT TO HARDWARE OFF */
/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
/* ~~~~~~~~PHASE LOOP LOCKED PLLCLK->56MHz ~~~~ */
RCC_PLLCmd(DISABLE); /* ENABLE/DISABLE RCC_CR.PLLON */
RCC_PLLConfig(RCC_PLLSource_HSE_Div1,RCC_PLLMul_9); /*
SYSCLK=72MHZ- RCC_CFGR.PLLSRC=1, RCC_CFGR.PLLXRPRE=0 y RCC_CFGR.PLLMULL=0111 */
RCC_PLLCmd(ENABLE); /* ENABLE/DISABLE RCC_CR.PLLON */
while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET); /* WAIT TO HARDWARE OFF */
/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
/* ~ SYSTEM CLOCK SYSCLK=72MHZ HCLK=72MHZ ~~~~ */
RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_1Div5); /* RELOJ DEL USB - 72MHz/1.5=48MHZ */
RCC_ADCCLKConfig(RCC_PCLK2_Div8); /* RELOJ DEL ADC PCLK2/8=9MHz - CONFIGURE RCC_CFGR.ADCPRE */
RCC_PCLK2Config(RCC_HCLK_Div1); /* CONFIGURE RCC_CFGR.PPRE2 APB2
PCLK2=72MHz */
RCC_PCLK1Config(RCC_HCLK_Div2); /* CONFIGURE RCC_CFGR.PPRE1 APB1
PCLK1=36MHz */
RCC_HCLKConfig(RCC_SYSCLK_Div1); /* CONFIGURE RCC_CFGR.HPRE AHB
HCLK=72MHz*/
/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ EMB_FLASH ~~~~ */
#ifdef EMB_FLASH
// 5. Init Embedded Flash
// Zero wait state, if 0 < HCLK 24 MHz
// One wait state, if 24 MHz < HCLK 56 MHz
// Two wait states, if 56 MHz < HCLK 72 MHz
// Flash wait state
FLASH_SetLatency(FLASH_Latency_2);
// Half cycle access
FLASH_HalfCycleAccessCmd(FLASH_HalfCycleAccess_Disable);
// Prefetch buffer
FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
#endif // EMB_FLASH
/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
// 5. Clock system from PLL
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); /* SELECCIONA EL CLOCK DEL PLL - MODIFICA RCC_CFGR.SW */
}
/* ============================================================ */
/* ============================================================ */void GPIO_configuration(void) {
GPIO_InitTypeDef GPIO_InitStructure;
/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ GPIO INIT ~~~ */
#define sysclk 0x04000000
#define HSIclk 0x05000000
#define HSEclk 0x06000000
#define PLLdiv2 0x07000000 /* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
/* ~~~~~ OUTPUT PINS ~~~~~ */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA,ENABLE); /* ENABLE CLK PORTS */
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA,DISABLE); /* NO RESET PORTS */
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; /* MAX VEL ESCRITURA */
GPIO_InitStructure.GPIO_Mode =
GPIO_Mode_AF_PP; /* ALTERNATE OUTPUT PUSH-PULL */
GPIO_InitStructure.GPIO_Pin =
GPIO_Pin_8;
GPIO_Init(
GPIOA, &GPIO_InitStructure);
RCC->CFGR |= sysclk;
}
/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
I configure the PA.8 pin as ALTERNATE OUTPUT PUSH-PULL like RM0008 on pag 147.
Then I configure RCC_CFGR.MCO with some diferents values to watch the microcontroller clock output, like RM0008 in pag 85.
I´m doing well??
I see on oscilloscope the sysclk signal to 72MHz. It varies between 71,70Mhz to 72,70MHz in instant measures, and in average mode, i see 72,30MHz.
Is it normal??
