I am running code on an STM32U585QI that enters STOP2 when the code is idle. I am disabling the data cache before going to stop2, and enabling it when coming out (to deal with an errata item). My code basically does this:
HAL_DCACHE_DeInit();
HAL_PWREx_EnterSTOP2Mode();
HAL_DCACHE_Init();
My question is, should I tell the CM33 to synchronize before/after this as well? Like this?
HAL_DCACHE_DeInit();
__DSB();
HAL_PWREx_EnterSTOP2Mode();
__ISB();
HAL_DCACHE_Init();
(those are cmsis_gcc.h functions to make the equivalent "dsb" and "isb" assembly calls)
